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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75237
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The PD75237 is a microcomputer with a CPU capable of 1-, 4-, and 8-bit-wise data processing, a ROM, a RAM, I/O ports, a fluorescent display tube (FIP (R)) controller/driver, A/D converters, a watch timer, a timer/pulse generator capable of outputting 14-bit PWM, a serial interface and a vectored interrupt function integrated on a single-chip. The PD75237 has the more improved peripheral functions including the RAM capacity, FIP controller/driver display capabilities, I/O ports, A/D converter and serial interface than those of the PD75217. The PD75237 is most suited for advanced and popular VCR timer and tuner applications, single-chip configurations of system computers, advanced CD players and advanced microwave ovens. The PD75P238 PROM product and various types of development tools (IE-75001-R, assemblers and others) are available for evaluation in system development or small-volume production.
FEATURES
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Built-in, large-capacity ROM and RAM * Program memory (ROM): 24K x 8 * Data memory (RAM): 1K x 4 I/O port: 64 ports (except FIP dedicated pins) Minimum instruction execution time: 0.67 s (when operated at 6.0 MHz) Instruction execution time varying function to achieve a wide range of power supply voltages Built-in programmable FIP controller/driver * Number of segments: 9 to 24 * Number of digits: 9 to 16
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8-bit A/D converter: 8 channels Powerful timer/counter function: 5 channels 8-bit serial interface: 2 channels Interrupt function with importance attached to applications Product with built-in PROM: PD75P238
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ORDERING INFORMATION
Ordering Code Package 94-pin plastic QFP (20 x 20 mm) Quality Grade Standard
PD75237GJ-xxx-5BG
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The information in this document is subject to change without notice. Document No. IC-2807A (O. D. No. IC-8009A) Date Published March 1993 P Printed in Japan The mark 5 shows major revised points. (c) NEC Corporation 1991
PD75237
LIST OF PD75237 FUNCTIONS
Item Built-in memory capacity ROM: 24448 x 8 bits, RAM: Function 1024 x 4bits
I/O line except FIP dedicated pins
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(
)
64 lines
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Input pin : 16 Input/output pin : 24 Output pin : 24
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Instruction cycle
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0.67 s/1.33 s/2.67 s/10.7 s (when operated at 6.0 MHz) 0.95 s/1.91 s/3.82 s/15.3 s (when operated at 4.19 MHz) 122 s (when operated at 32.768 kHz) Number of segments : 9 to 24 Number of digits : 9 to 16 Dimmer function : 8 levels Pull-down resistor mask option Key scan interrupt generation enabled
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Fluorescent display tube (FIP) controller/driver
q q q q
Timer/counter
5 channels
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Basic interval timer : Watchdog timer applicable Timer/event counter Watch timer : Buzzer output enabled Timer/pulse generator : 14-bit PWM output enabled Event counter SBI/3-wire type 3-wire type
Serial interface
2 channels
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Multi-interrupt enabled by hardware
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External interrupt:
3 interrupts
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External test input:
1 input
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Interrupt
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Internal interrupt:
5 interrupts
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Internal test input:
2 inputs
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Both-edge detection Detected edge programmable (with noise remove function) Detected edge programmable Rising edge detection Timer/pulse generator Timer/event counter Basic interval timer Serial interface #0 Key scan interrupt Clock timer Serial interface #1
System clock oscillator
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Main system clock Subsystem clock
: 6.0 MHz, 4.19 MHz : 32.768 kHz standard : Pull-down resistor or open-drain output : Pull-up resistors : Pull-down resistor
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Mask option
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High withstand voltage port Ports 4 and 5 Port 7
Operating temperature range Operating voltage Package
-40 to +85 C 2.7 to 6.0 V (standby data hold: 2.0 to 6.0 V) 94-pin plastic QFP (20 x 20 mm)
2
PD75237
PIN CONFIGURATION
AN1 AN2 AN3 AN4/P90 AN5/P91 AN6/P92 AN7/P93 AVSS RESET P00/INT4 P01/SCK0 P02/SO0/SB0 P03/SI0/SB1 P10/INT0 P11/INT1 P12/INT2 P13/TI0 P20/PTO0 P21 P22/PCL P23/BUZ P30 P31
AN0 AVREF AVDD VDD VDD X2 X1 IC XT2 XT1 VSS S16/P100 S17/P101 S18/P102 S19/P103 S20/P110 S21/P111 S22/P112 S23/P113 S0/P120 S1/P121 S2/P122 S3/P123
94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 7372 71 1 70 2 69 3 68 4 67 5 66 6 65 7 64 8 63 9 62 10 61 11 60 12 59 13 58 14 57 15 56 16 55 17 54 18 53 19 52 20 51 21 50 22 49 23 48 24 2526272829303132333435363738 39404142434445 4647
P32 P33 P40 P41 P42 P43 VSS P50 P51 P52 P53 P60 P61 P62 P63 P70 P71 P72 P73 P80/PPO P81/SCK1 P82/SO1 P83/SI1 VDD
Note
Be sure to supply power to AVDD , VDD , VSS and AVSS pins (pin Nos. 3, 4, 5, 11, 30, 48, 65 and 87) . Connect the IC (Internally Connected) pin to GND.
Remarks
S4/P130 S5/P131 S6/P132 S7/P133 S8/P140 S9/P141 VDD VLOAD T15/S10/P142 T14/S11/P143 PH0/T13/S12/P150 PH1/T12/S13/P151 PH2/T11/S14/P152 PH3/T10/S15/P153 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0
PD75237GJ-xxx-5BG
3
4
BASIC INTERVAL TIMER TI0 TI0/P13 PTO0/P20 INTBT TIMER/EVENT COUNTER #0 INTT0 BUZ/P23 WATCH TIMER INTW GENERAL REG. PPO/P80 TIMER/PULSE GENERATOR INTTPG SI0/SB1/P03 SO0/SB0/P02 SCK0/P01 SERIAL INTERFACE0 INTCSI SI1/P83 SO1/P82 SCK1/P81 INT0/P10 INT1/P11 INT2/P12 INT4/P00 TI0 EVENT COUNTER AN0-AN3 AN4/P90-AN7/P93 AVDD AVREF AV SS 8 A/D CONVERTER PCL/P22 XT1XT2 X1 X2 RESET VDD VSS VDD ROM PROGRAM MEMORY 24448x8 BANK PROGRAM COUNTER (15) ALU CY SP (8) SBS (2) PORT0 PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORT7 DECODE AND CONTROL PORT8 RAM DATA MEMORY 1024x4 PORT9 4 4 4 4 4 4 4 4 4 4 10 4 SERIAL INTERFACE1 fx/2N 8 INTERRUPT CONTROL CLOCK OUTPUT CONTROL CLOCK DIVIDER CLOCK GENERATOR SUB MAIN STAND BY CONTROL CPU CLOCK PORT10-15 24 FIP CONTROLLER/ DRIVER 2 10 P00-P03 P10-P13 P20-P23 P30-P33 P40-P43* P50-P53* P60-P63 P70-P73 P80-P83 P90-P93 T0-T9 T10/S15/PH3/P153T13/S12/PH0/P150 T14/S11/P143T15/S10/P142 S0/P120-S9/P141 VLOAD P100-P153 BIT SEQ. BUFFER(16)
S16/P100-S23/P113
BLOCK DIAGRAM
PD75237
*
PORT4 and PORT5 are 10 V middle-high voltage N-ch open-drain input/output ports.
PD75237
CONTENTS 1. PIN FUNCTIONS ......................................................................................................................................... 7
1.1 1.2 1.3 1.4 PORT PINS ........................................................................................................................................................... 7 NON-PORT PINS .................................................................................................................................................. 9 PIN INPUT/OUPUT CIRCUIT LIST ................................................................................................................... 11 RECOMMENDED CONNECTIONS OF PD75237 UNUSED PINS ............................................................... 15
2.
PD75237 ARCHITECTURE AND MEMORY MAP................................................................................ 16
2.1 2.2 2.3 DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODE ..................................................... 16 GENERAL REGISTER BANK CONFIGURATION ............................................................................................ 19 MEMORY MAPPED I/O .................................................................................................................................... 22
3.
INTERNAL CPU FUNCTIONS .................................................................................................................. 28
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 PROGRAM COUNTER (PC): 15 BITS .............................................................................................................. PROGRAM MEMORY (ROM): 24448 WORDS x 8 BITS ............................................................................... DATA MEMORY ................................................................................................................................................ GENERAL REGISTER: 8 x 4 BITS x 4 BANKS ............................................................................................... ACCUMULATOR ............................................................................................................................................... STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS) ....................................................... PROGRAM STATUS WORD (PSW): 8 BITS ................................................................................................... BANK SELECT REGISTER (BS) ....................................................................................................................... 28 28 30 32 33 33 36 40
4.
PERIPHERAL HARDWARE FUNCTIONS ............................................................................................... 41
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 DIGITAL INPUT/OUTPUT PORTS ................................................................................................................... 41 CLOCK GENERATOR ........................................................................................................................................ 50 CLOCK OUTPUT CIRCUIT ................................................................................................................................ 58 BASIC INTERVAL TIMER ................................................................................................................................. 61 TIMER/EVENT COUNTER ................................................................................................................................ 63 WATCH TIMER .................................................................................................................................................. 69 TIMER/PULSE GENERATOR ........................................................................................................................... 71 EVENT COUNTER ............................................................................................................................................. 77 SERIAL INTERFACE .......................................................................................................................................... 79 A/D CONVERTER ........................................................................................................................................... 113 BIT SEQUENTIAL BUFFER: 16 BITS ............................................................................................................. 119 FIP CONTROLLER/DRIVER ............................................................................................................................ 119
5.
INTERRUPT FUNCTIONS ...................................................................................................................... 131
5.1 5.2 5.3 5.4 5.5 INTERRUPT CONTROL CIRCUIT CONFIGURATION ................................................................................... INTERRUPT CONTROL CIRCUIT HARDWARE DEVICES ........................................................................... INTERRUPT SEQUENCE ................................................................................................................................ MULTI-INTERRUPT SERVICE CONTROL ..................................................................................................... VECTOR ADDRESS SHARING INTERRUPT SERVICING ........................................................................... 131 133 138 139 141
6.
STANDBY FUNCTIONS ......................................................................................................................... 142
6.1 6.2 6.3 STANDBY MODE SETTING AND OPERATING STATE .............................................................................. 142 STANDBY MODE RELEASE .......................................................................................................................... 144 OPERATION AFTER STANDBY MODE RELEASE ....................................................................................... 146
5
PD75237
7. 8.
RESET FUNCTIONS ............................................................................................................................... 147 INSTRUCTION SET ................................................................................................................................ 150
8.1 8.2 8.3 CHARACTERISTIC INSTRUCTIONS OF PD75237 ..................................................................................... 150 INSTRUCTION SET AND OPERATION ......................................................................................................... 153 OPERATION CODES ....................................................................................................................................... 162
9.
MASK OPTION SELECTION ................................................................................................................. 168
10. APPLICATION BLOCK DIAGRAM ........................................................................................................ 169 11. ELECTRICAL SPECIFICATIONS ........................................................................................................... 170 5 12. CHARACTERISTIC CURVES (REFERENCE VALUES) ........................................................................ 183 13. PACKAGE INFORMATION ................................................................................................................... 185 14. RECOMMEDED SOLDERING CONDITIONS ....................................................................................... 186 APPENDIX A. APPENDIX B. LIST OF PD75238 SERIES PRODUCT FUNCTIONS..................................................... 187 DEVELOPMENT TOOLS ................................................................................................... 188
6
PD75237
1. PIN FUNCTIONS
1.1 PORT PINS (1/2)
Pin Name P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30 *2 P31 *2 P32 *2 P33 *2 *2 P40 to P43
I/O
DualFunction Pin INT4
Function
Input / Output 8-Bit After Reset Circuit Type *1 I/O B
Input
SCK0 SO0/SB0 SI0/SB1 INT0
4-bit input port (PORT0). Built-in pull-up resistor can be specified in 3-bit units by software for P01 to P03. Noise removing function available 4-bit input port (PORT1). Built-in pull-up resistor can be specified in 4-bit units by software.
x
F -A Input F -B M-C
Input
INT1 INT2 TI0 PTO0
x
Input
B -C
Input/ output
-- PCL BUZ --
4-bit input/ output port (PORT2). Built-in pull-up resistor can be specified in 4-bit units by software.
x
Input
E-B
Input/ output
-- -- --
Programmable 4-bit input/ output port (PORT3). Input/ output specifiable in 1-bit units. Built-in pull-up resistor can be specified in 4-bit units by software. N-ch open-drain 4-bit input/output port (PORT4). Pull-up resistor can be incorporated in 1-bit units (mask option). 10 V withstand voltage with open drain.
x
Input
E-C
Input/ output
--
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*2 P50 to P53 Input/ output -- N-ch open-drain 4-bit input/ output port (PORT5). Pull-up resistor can be incorporated in 1-bit units (mask option). 10 V withstand voltage with open drain. Programmable 4-bit input/output port (PORT6). Input/output specifiable in 1-bit units. Built -in pull-up resistor can be specified in 4-bit units by software.
High level (when a pullup resistor is incorporated) or high impedance High level (when a pullup resistor is incorporated) or high impedance
M
M
P60 P61 P62 P63 P70 P71 P72 P73 Input/ output Input/ output
-- -- -- -- -- -- -- --
Input
E-C
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4-bit input/output port (PORT7). Built-in pull-down resistor can be incorporated in 1-bit units (mask option).
VSS level (when a pulldown resistor is incorporated) or high impedance
V
* 1. 2.
Schmitt trigger inputs are circled. Can drive LED directly.
7
PD75237
1.1
PORT PINS (2/2)
I/O Input/ output Input/ output Input/ output Input DualFunction Pin PPO Function 8-Bit After Reset I/O Input / Output Circuit Type * A
Pin Name
P80
P81
SCK1
4-bit input port (PORT8).
x
Input
F
P82 P83 P90 P91 P92 P93 P100 P101
SO1 SI1 AN4
E B
Input
AN5 AN6 AN7 S16 S17
4-bit input port (PORT9).
x
Input
Y-A
Output P102 P103 P110 P111 P112 P113 P120 P121 P122 P123 P130 P131 P132 P133 P140 P141 Output P142 P143 P150 P151 P152 P153 PH0 PH1 PH2 PH3 Output S14/T11/P152 S15/T10/P153 Output S14/T11/PH2 S15/T10/PH3 S12/T13/P150 S13/T12/P151 S10/T15 S11/T14 S12/T13/PH0 S13/T12/PH1 Output Output S2 S3 S4 S5 S6 S7 S8 S9 Output S18 S19 S20 S21 S22 S23 S0 S1
P-ch open-drain 4-bit high-voltage output port. Pull-down resistor can be incorporated (mask option).
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P-ch open-drain 4-bit high-voltage output port. Pull-down resistor can be incorporated (mask option).
VLOAD level (when a pulldown resistor to VLOAD is incorporated), VSS level (when a pulldown resistor to VSS is incorporated) or high impedance
I-F
P-ch open-drain 4-bit high-voltage output port. Pull-down resistor can be incorporated (mask option).
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P-ch open-drain 4-bit high-voltage output port. Pull-down resistor can be incorporated (mask option).
VLOAD level (when a pulldown resistor to VLOAD is incorporated) or high impedance
P-ch open-drain 4-bit high-voltage output port. Pull-down resistor can be incorporated (mask option). P142 and P143 can drive LED directly.
I-C
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P-ch open-drain 4-bit high-voltage output port. Pull-down resistor can be incorporated (mask option). These ports can drive LED directly.
P-ch open-drain 4-bit high-voltage output port. Pull-down resistor can be incorporated (mask option).
x
* 8
Schmitt trigger inputs are circled.
PD75237
1.2
NON-PORT PINS (1/2)
DualFunction Pin -- Input / Output Circuit Type *
Pin Name
I/O
Function Digit output high-voltage highcurrent output pins. Digit/segment output dual-function high-voltage high-current output pins. Extra pins can be used as PORTH. These pins can be used as PORT15 in the static mode. Digit/segment output dual-function high-voltage high-current output pins. These pins can be used as POTR14 in the static mode. FIP controller/driver output pins. Segment high-voltage output Pull-down resistor can pins. be incorporated in bit These pins can be used as units (mask option). PORT12 to PORT14 in the static mode.
After Reset
T0 to T9
T10/S15 to T13/S12
PH3/P153 to PH0/P150
T14/S11
P143
T15/S10
P142 P120 to
VLOAD level (when a pull-down resistor to VLOAD is incorporated) or high impedance.
I-C
S0 to S3 P123 Output S4 to S7 P133 S8 S9 P140 P141 P130 to
S16 to S19
P100 to P103 Segment high-voltage output pins. These pins can be used as PORT10 and PORT11 in the static mode.
P110 to S20 to S23 P113
VLOAD level (when a pull-down resistor to VLOAD is incorporated), VSS level (when a pull-down resistor to VSS is incorporated) or high impedance
I-F
TI0 PTO0 PCL BUZ
Input Output Output Output Input/ output Input/ output Input/ output
P13 P20 P22 P23
External event pulse input to timer/event counter #0 and event counter #1. Timer/event counter output. Clock output. Fixed frequency output (for buzzer or system clock trimming). Serial clock input/output. Serial data output. Serial bus input/output. Serial data input. Serial bus input/output.
-- Input Input Input
B -C E-B E-B E-B
SCK0
P01
Input
F -A
SO0/SB0
P02
Input
F -B
SI0/SB1
P03
Input
M-C
*
Schmitt trigger inputs are circled.
9
PD75237
1.2
NON-PORT PINS (2/2)
DualFunction Pin Input / Output Circuit Type *
Pin Name
I/O
Function
After Reset
INT4
Input
P00
Edge-detected vectored interrupt input (valid for detection of rising and falling edges).
--
B
INT0 Input INT1 Input INT2 Input/ output Output Input Input AN4 to AN7 AVDD AVREF AVSS -- Input --
P10
Edge-detected vectored interrupt input (detected edge selection possible).
Clocked -- Asynchronous B -C
P11 Edge-detected testable input (rising edge detection).
P12
Asynchronous
--
B -C
SCK1 SO1 SI1 AN0 to AN3
P81 P82 P83 -- P90 to P93 -- -- --
Serial clock input/output. Serial data output. Serial data input. Analog input to A/D converter. A/D converter power supply. A/D converter reference voltage input. A/D converter reference GND potential. Main system clock oscillation crystal/ceramic connection. An external clock is input to X1 and an antiphase clock is input to X2. Subsystem clock oscillation crystal connection. An external clock is input to XT1 and XT2 is made open. System reset input. Timer/pulse generator pulse output. Positive power supply. GND potential. FIP controller/driver pull-down resistor connect/power supply.
Input Input Input -- -- -- --
F E B Y Y-A -- Z --
X1, X2
Input
--
--
--
XT1 XT2 RESET PPO VDD (3 - Pin) VSS (2 - Pin) VLOAD
Input -- -- Input Output -- P80 -- -- --
-- -- Input -- -- --
-- B -- -- -- --
-- -- --
*
Schmitt trigger inputs are circled.
10
PD75237
1.3
PIN INPUT/OUTPUT CIRCUIT LIST (1/4)
TYPE A
TYPE D
VDD
VDD
P-ch IN
data
P-ch OUT
N-ch
output disable
N-ch
CMOS-Specified Input Buffer
Push-Pull Output which can be Set to Output High Impedance (with Both P-ch and N-ch Set to OFF)
TYPE B
TYPE E
data output disable
IN
IN/OUT Type D
Type A
Schmitt Trigger Input Having Hysteresis Characteristics
Input/Output Circuit Consisting of Type D Push-Pull Output and Type A Input Buffer
TYPE B-C
VDD
TYPE E-B
VDD P.U.R
P.U.R P-ch P.U.R enable
data
output disable
P-ch
IN/OUT Type D
IN
output disable
P.U.R:Pull-Up Resistor
Schmitt Trigger Input Having Hysteresis Characteristics
Type A
P.U.R:Pull-Up Resistor
11
PD75237
1.3
PIN INPUT/OUTPUT CIRCUIT LIST (2/4)
TYPE E-C
VDD P.U.R
TYPE F-B
VDD P.U.R P.U.R enable P-ch VDD P-ch IN/OUT
P.U.R enable
P-ch
output disable (P-ch)
data Type D output disable
IN/OUT
data output disable output disable (N-ch) N-ch
Type A
Type B
P.U.R:Pull-Up Resistor
P.U.R:Pull-Up Resistor
TYPE F
TYPE F-C
VDD P.U.R
data Type D output disable
IN/OUT
P.U.R enable data Type D
P-ch IN/OUT
Type B
output disable
Input/Output Circuit Consisting of Type D Push-Pull Output and Type B Schmitt Trigger Input
Type B
P.U.R:Pull-Up Resistor
TYPE F-A
VDD P.U.R
TYPE I-C
VDD VDD
P.U.R enable data Type D output disable
P-ch
data P-ch P-ch OUT N-ch P.D.R (Mask Option) VLOAD
IN/OUT
Type B
P.D.R:Pull-Down Resistor
P.U.R:Pull-Up Resistor
12
PD75237
1.3
PIN INPUT/OUTPUT CIRCUIT LIST (3/4) TYPE I-F
VDD VDD
TYPE V
data IN/OUT
data P-ch P-ch OUT N-ch P.D.R (Mask Option) VLOAD
Type D output disable
Type A P.D.R (Mask Option)
P.D.R:Pull-Down Resistor
P.D.R:Pull-Down Resistor
TYPE M
P.U.R (Mask Option)
VDD
TYPE Y
AVDD
IN/OUT
P-ch
data output disable N-ch
IN AVDD Sampling C
N-ch
AVSS AVSS
Middle-High Voltage Input Buffer
AVSS
Reference Voltage (from the Series Resistance String Voltage Tap)
P.U.R:Pull-Up Resistor
TYPE M-C
VDD P.U.R P.U.R enable P-ch IN/OUT
IN
TYPE Y-A
AVDD P-ch
data output disabie
N-ch
AVDD
N-ch AVSS AVSS
Sampling C
AVSS
Type B P.U.R:Pull-Up Resistor
Reference Voltage (from the Series Resistance String Voltage Tap)
13
PD75237
1.3
PIN INPUT/OUTPUT CIRCUIT LIST (4/4)
TYPE Z
AVss
14
PD75237
RECOMMENDED CONNECTIONS OF PD75237 UNUSED PINS
Pin P00/INT4 P01/SCK0 P02/SO0/SB0 P03/SI1/SB1 P10/INT0 to P12/INT2 Connect to VSS P13/TI0 P20/PTO0 P21 P22/PCL P23/BUZ P30 to P33 P40 to P43 P50 to P53 P60 to P63 P70 to P73 P80/PPO P81/SCK1 P82/SO1 P83/SI1 P90/AN4 to P93/AN7 P100/S16 to P103/S19 P110/S20 to P113/S23 P120 to P123 Leave open P130 to P133 P140 to P143 P150 to P153 AN0 to AN3 AVREF AVDD AVSS XT1 XT2 VLOAD Connect to VDD Connect to VSS Connect to VSS or VDD Leave open Connect to VSS Connect to VSS Connect to VSS Ouput state : Leave open Input state : Connect to VSS or VDD Connect to VSS or VDD Connect to VSS Recommended Connection
1.4
15
PD75237
2. PD75237 ARCHITECTURE AND MEMORY MAP
The PD75237 has the following three architectural features. (a) (b) (c) Data memory bank configuration General register bank configuration Memory mapped I/O
Each feature is outlined below.
2.1
DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODE
As shown in Fig. 2-1, the PD75237 incorporates a static RAM (928 words x 4 bits) at addresses 000H to 19FH and 200H to 3FFH in the data memory space and a display data memory (96 words x 4 bits) at addresses 1A0H to 1FFH and peripheral hardware (input/output ports, timers, etc.) at addresses F80H to FFFH. For addressing of this 12-bit address data memory space, the memory bank has a configuration wherein the lower 8 bits are directly or indirectly specified by an instruction and the higher 4-bit address is specified by a memory bank (MB). A memory bank enable flag (MBE) and a memory bank select register (MBS) are incorporated to specify the memory bank (MB) and addressing operations shown in Fig. 2-1 and Table 2-1 can be carried out. (MBS is a register to select the memory bank and can set 0, 1, 2, 3 and 15. MBE is a flag to determine whether the memory bank selected by MBS should be validated or not. Since MBE is automatically saved/reset for interrupt or subroutine processing, it can be freely set for either processing.) For data memory space addressing, set MBE = 1 normally and manipulate the memory bank static RAM specified by MBS. Efficient programming is possible by using the MBE = 0 or MBE = 1 mode for each program processing.
Applicable Program Processing Interrupt service Processing of repeating built-in hardware manipulation and static RAM manipulation Subroutine processing Normal program processing
MBE = 0 mode
MBE = 1 mode
16
PD75237
Fig. 2-1 Date Memory Configuration and Addressing Range in Each Addressing Mode
Addressing Mode Memory Bank Enable Flag 000H 01FH 020H 07FH Data Area Static RAM (Memory Bank 0) General Register Area
mem mem. bit MBE =0 MBE =1
@HL @H+mem. bit MBE =0 MBE =1
@DE @DL --
Stack pmem. Address- fmem. bit @L ing -- -- --
MBS =0
MBS =0
SBS =0
0FFH 100H Data Area Static RAM (Memory Bank 1) Display Data Memory Area 1FFH 200H Stack Area Data Area Static RAM (Memory Bank 2) 2FFH 300H
19FH 1A0H
MBS =1
MBS =1
SBS =1
MBS =2
MBS =2
SBS =2
Data Area Static RAM (Memory Bank 3) 3FFH
MBS =3
MBS =3
SBS =3
Not Incorporated
F80H
FC0H
Peripheral Hardware Area (Memory Bank 15)
MBS = 15
MBS = 15
FFFH
Remarks
-- : Don't care
17
PD75237
Table 2-1 Addressing Modes
Addressing Mode
Identifier
Address Specified Bit indicated by bit of address indicated by MB and mem, where: When mem = 00H to 7FH, MB = 0 MBE = 0 When mem = 80H to FFH, MB = 15 MBE = 1 MB = MBS Address indicated by MB and mem, where : When mem = 00H to 7FH, MB = 0 MBE = 0 When mem = 80H to FFH, MB = 15 MBE = 1 MB = MBS
1-bit direct addressing
mem.bit
4-bit direct addressing mem
8-bit direct addressing
Address indicated by MB and mem (mem is an even address), where: When mem = 00H to 7FH, MB = 0 MBE = 0 When mem = 80H to FFH, MB = 15 MBE = 1 MB = MBS @HL Address indicated by MB and HL, where : MB = MBE* MBS Address indicated by MB and HL, where : MB = MBE* MBS HL+ automatically increments L register after addressing. HL- automatically decrements L register after addressing. Address indicated by DE of memory bank 0 Address indicated by DL of memory bank 0 Address indicated by MB and HL, where : MB = MBE* MBS Bit 0 of L register is ignored. Bit indicated by bit of address indicated by fmem, where: FB0H to FBFH (interrupt-related hardware) fmem = FF0H to FFFH (I/O port) Bit indicated by the lower 2 bits of L register of the address indicated by the higher 10 bits of pmem and the higher 2 bits of L register, where: pmem = FC0H to FFFH Bit indicated by bit of the address indicated by MB, H and the lower 4 bits of mem, where: MB = MBE* MBS Address indicated by SP of memory banks 0, 1, 2 and 3 selected by SBS
@HL+ @HL- 4-bit register indirect addressing @DE @DL 8-bit register indirect addressing
@HL
fmem.bit
Bit manipulation addressing
pmem.@L
@H + mem.bit
Stack addressing
As described in Table 2-1, direct and indirect addressing is possible for each of 1-bit, 4-bit and 8-bit data in PD75237 data memory manipulation. Thus, easy-to-understand programs can be created very efficiently.
18
PD75237
2.2
GENERAL REGISTER BANK CONFIGURATION
The PD75237 incorporates four register banks, each bank consisting of eight general registers, X, A, B, C, D, E, H and L. This general register area is mapped at addresses 00H to 1FH of the memory bank 0 of the data memory (refer to Fig. 2-2 General Register Configuration (4-Bit Processing)). A register bank enable flag (RBE) and a register bank select register (RBS) are incorporated to specify the above general register banks. RBS is a register to select a register bank and RBE is a flag to determine whether the register bank selected by RBS should be validated or not. The register bank (RB) which is validated for instruction execution is given as RB = RBE* RBS. As described above, with the PD75237 having four register banks, programs can be created very efficiently by using different register banks for normal processing and interrupt service as described in Table 2-2. (RBE is automatically saved and set for interrupt service and automatically reset upon termination of the interrupt service.) Table 2-2 Recommended Use of Register Banks in Normal and Interrupt Routines
Normal processing Single interrupt service Double interrupt service Triple or more interrupt service
Use register banks 2 and 3 with RBE = 1. Use register bank 0 with RBE = 0. Use register bank 1 with RBE = 1. (It is necessary to save/reset RBS.) Save/reset registers by PUSH and POP.
Not only in 4-bit units, a register pair of XA, HL, DE or BC can transfer, compare, operate, increment or decrement data in 8-bit units. In this case, register pairs with the reversed bit 0 of the register bank specified by RBE*RBS can be specified as XA', HL', DE' and BC'. Thus, the PD75237 has eight 8-bit registers (refer to Fig. 2-3 General Register Configuration (8-Bit Processing)).
19
PD75237
Fig. 2-2 General Register Configuration (4-Bit Processing)
X
01H
A
00H
H D
03H
L E
02H
Register Bank 0 (RBE*RBS = 0)
04H
05H
B
07H
C
06H
X
09H
A
08H
H
0BH
L
0AH
D
0DH
E
Register Bank 1 (RBE*RBS = 1)
0CH
B
0FH
C
0EH
X
11H
A
10H
H
13H
L
12H
D
15H
E
Register Bank 2 (RBE*RBS = 2)
14H
B
17H
C
16H
X
19H
A
18H
H D
1BH
L E
1AH
Register Bank 3 (RBE*RBS = 3)
1CH
1DH
B
1FH
C
1EH
20
PD75237
Fig. 2-3 General Register Configuration (8-Bit Processing)
XA
00H
XA'
00H
HL DE
02H
HL' DE'
02H
04H
04H
BC
06H
BC' When RBE*RBS = 0 XA
06H
When RBE*RBS = 1
08H
XA'
08H
HL'
0AH
HL
0AH
DE'
0CH
DE
0CH
BC'
0EH
BC
0EH
XA
10H
XA'
10H
HL DE
12H
HL' DE'
12H
14H
14H
BC
16H
BC' When RBE*RBS = 2 XA
16H
When RBE*RBS = 3
18H
XA'
18H
HL'
1AH
HL
1AH
DE'
1CH
DE
1CH
BC'
1EH
BC
1EH
21
PD75237
2.3
MEMORY MAPPED I/O
As shown in Fig. 2-1, the PD75237 employs the memory mapped I/O with the peripheral hardware including input/output ports and timers mapped at addresses F80H to FFFH in the data memory space. Thus, there are no special instructions to control the peripheral hardware and all operations are controlled by memory manipulation instructions. (Some hardware control mnemonics are available to make the program easy to understand.) When operating the peripheral hardware, the addressing modes listed in Table 2-3 can be used. Manipulate the display data memory, key scan register and port H mapped at addresses 1A0H to 1FFH by specifying memory bank 1. Table 2-3 Addressing Modes Applicable when Operating the Peripheral Hardware at Addresses F80H to FFFH
Applicable Addressing Mode Specify by direct addressing mem.bit with MBE = 0 or (MBE = 1, MBS = 15) Bit manipulation Specify by direct addressing fmem.bit irrespective of MBE and MBS Specify by indirect addressing pmem.@L irrespective of MBE and MBS Specify by direct addressing mem with MBE = 0 or (MBE = 1, MBS = 15) 4-bit manipulation Specify by register indirect addressing @HL with (MBE = 1, MBS = 15) Specify by direct addressing mem with MBE = 0 or (MBE = 1, MBS = 15) (mem is an even address.) 8-bit manipulation Specify by register indirect addressing @HL with MBE = 1 and MBS = 15 (L register contents are even.) Applicable Hardware All hardware devices enabled for bit manipulation IST0, IST1, MBE, RBE, IExxx, IRQxxx, PORTn. 0 to 3 PORTn.
All hardware devices enabled for 4-bit manipulation
All hardware devices enabled for 8-bit manipulation
Table 2-4 shows the PD75237 I/O map. In the table, each item has the following meanings: * Symbol ............. Name indicating the on-chip hardware address. Can be described in the instruction operand column. * R/W ................... Indicates whether the corresponding hardware is enabled for read/write. R/W : Read/write enable R : Read only W : Write only * No. of manipulatable bits ........ Indicates the number of applicable bits before operating the corresponding hardware. * Bit manipulated addressing .... Indicates the applicable bit manipulated addressing before operating the applicable hardware.
22
PD75237
Table 2-4 PD75237 I/O Map (1/5)
Hardware Name (Symbol) Address F80H Stack pointer (SP) F82H F83H F84H Register bank select register (RBS) R*1 Memory bank select register (MBS) Stack bank select register (SBS) Basic interval timer mode register (BTM) R/W R/W R/W b3 b2 b1 b0
No. of Manipulatable Bits Bit Manipulated Addressing 1 Bit 4 Bits 8 Bits -- -- -- -- -- q q q q -- q
Remarks
Be sure to write 0 to bit 0.
*2 Be sure to write 0 to bits 3 and 2. mem.bit Only bit 3 is bit-manipulatable.
5
F85H F86H
W
v
q
--
Basic interval timer (BT)
R W W R/W
-- -- -- v
-- q q q
q -- -- -- mem.bit Only bit 3 is bittestable. Only bit 3 is bit-manipulatable.
F88H F89H F8AH
Display mode register (DSPM) Dimmer select register (DIMS) KSF Digit select register (DIGS)
F90H
Timer pulse generator mode register (TPGM) Timer pulse generator modulo register L (MODL) Timer pulse generator modulo register H (MODH) Watch mode register (WM)
W
v
v
q
mem.bit
F94H
R/W
--
--
q
F96H
R/W
--
--
q
F98H W -- -- q
* 1. 2.
Can be read/written by the SEL instruction. Individually manipulatable as RBS and MBS by 4-bit manipulation. Manipulatable as BS by 8-bit manipulation.
23
PD75237
Table 2-4 PD75237 I/O Map (2/5)
Hardware Name (Symbol) Address FA0H R/W b3 b2 b1 b0 W
No. of Manipulatable Bits Bit Manipulated Addressing 1 Bit 4 Bits 8 Bits v -- -- q -- -- -- -- q q --
Remarks Only bit 3 is bit-manipulatable.
Timer/event counter 0 mode register (TM0) TOE0 Timer/event counter 0 count register (T0) Timer/event counter 0 modulo register (TMOD0) Event counter mode register (TM1) Gate control register (GATEC) Counter register (T1)
FA2H FA4H
W R
FA6H
W
--
--
q
FA8H
v W -- W R -- --
-- q -- q -- -- q
Only bit 3 is bit-manipulatable.
FABH FACH
24
PD75237
Table 2-4 PD75237 I/O Map (3/5)
Hardware Name (Symbol) Address R/W b3 IST1 FB0H Program status word (PSW) FB2H FB3H FB4H FB5H FB7H FB8H FB9H FBAH FBBH FBCH FBDH FBEH FBFH IE1 IRQ1 IEKS IEW IRQKS IETPG IRQT1 IET0 Interrupt priority select register (IPS)
Processor clock control register (PCC)
b2 IST0
b1 MBE
b0 RBE R/W
No. of Manipulatable Bits Bit Manipulated Addressing 1 Bit 4 Bits 8 Bits q -- q q -- q -- q q q -- q -- q q -- q fmem.bit q -- q q q -- -- fmem.bit q q -- -- q q q q q q q q q
Remarks
W W W W W R/W R/W R/W R/W R/W R/W R/W R/W
5
INT0 mode register (IM0) INT1 mode register (IM1) System clock control register (SCC) IE4 IRQ4 IEBT IRQBT EOT IRQW IRQTPG IRQT0
Be sure to write 0 to bit 2. Be sure to write 0 to bits 3, 2 and 1. --
Only bits 3 and 0 are bit-manipulatable.
5
IECSI0 IRQCSI0 IE0 IE2 IRQ0 IRQ2
FC0H FC1H FC2H FC3H FC8H FC9H FCCH
Bit sequential buffer 0 (BSB0) Bit sequential buffer 1 (BSB1) Bit sequential buffer 2 (BSB2) Bit sequential buffer 3 (BSB3) CSIM11 CSIM10 CSIE1 Serial I/O shift register (SIO1)
R/W R/W R/W R/W W W R/W
q q q q -- q --
q q q q q q -- q -- -- q
5
25
PD75237
Table 2-4 PD75237 I/O Map (4/5)
Hardware Name (Symbol) Address FD0H FD4H R/W b3 b2 b1 b0 W W Clock output mode register (CLOM) Static mode register B (STATB)
No. of Manipulatable Bits Bit Manipulated Addressing 1 Bit 4 Bits 8 Bits -- -- q -- -- q
Remarks
FD6H
Static mode register A (STATA)
W
-- v
--
q
5
FD8H
SOC
EOC R/W
-- q -- -- q
A/D conversion mode register (ADM)
-- R --
Write only in 8-bit manipulation
FDAH SA register (SA) FDCH
Pull-up register specification register group A (POGA)
W
--
--
q
FE0H
Serial operating mode register (CSIM0) CSIE0 COI RELD WUP CMDT RELT
W R/W
-- q
-- q q mem.bit
Write only in 8-bit manipulation
FE2H
CMDD
SBI control register (SBIC) BSYE FE4H FE6H ACKD ACKE ACKT
R/W
q
--
--
mem.bit
Serial I/O shift register 0 (SIO0) Slave address register (SVA) PM33 PM32 PM31 PM30 Port mode register group A (PMGA) PM63 PM62 PM61 PM60 -- PM2 -- -- Port mode register group B (PMGB) PM7 -- PM5 PM4
R/W W
--
--
q
--
--
q
FE8H
W
--
--
q
FECH
W
--
--
q
26
PD75237
Table 2-4 PD75237 I/O Map (5/5)
Hardware Name (Symbol) Address FF0H FF1H FF2H FF3H FF4H FF5H FF6H FF7H FF8H FF9H FFAH FFBH FFCH FFDH FFEH FFFH R/W b3 b2 b1 b0 R R R/W R/W R/W R/W R/W R/W R R W W W W W W Port 0 (PORT0) Port 1 (PORT1) Port 2 (PORT2) Port 3 (PORT3) Port 4 (PORT4) Port 5 (PORT5) Port 6 (PORT6) Port 7 (PORT7) Port 8 (PORT8) Port 9 (PORT9) Port 10 (PORT10) Port 11 (PORT11) Port 12 (PORT12) Port 13 (PORT13) Port 14 (PORT14) Port 15 (PORT15)
No. of Manipulatable Bits Bit Manipulated Addressing 1 Bit 4 Bits 8 Bits q q q q q q q q q q q q q q q q q -- q q -- q q q q q q q q -- q q q q q q q q q q fmem.bit pmem.@L
Remarks
1A0H+4n 1A1H+4n 1BEH
Display data memory: S16 to S23 (n = 0 to 15)
R/W R/W R/W
q q q q q q q q q q q q
q q q q q q q q q q q q q q q q q q mem.bit
Key scan register (KS2) 1BFH 1C0H+4n 1C1H+4n 1C2H+4n 1C3H+4n 1FCH Key scan register (KS0) 1FDH 1FEH 1FFH Key scan register (KS1) Port H (PORTH) R/W R/W R/W Display data memory: S0 to S7 (n = 0 to 15) Display data memory: S8 to S15 (n = 0 to 15) R/W R/W R/W R/W R/W R/W
27
PD75237
3. INTERNAL CPU FUNCTIONS
3.1 PROGRAM COUNTER (PC): 15 BITS This is a 15-bit binary counter to hold the program memory address information. Fig. 3-1 Program Counter Configuration
PC14
PC13
PC12
PC11
PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
When RESET is input, the lower 6 bits at address 0000H and the contents at address 0001H of the program memory are set to PC13 to PC8 and PC7 to PC0, respectively, and the PC is initialized. The reset start address should therefore be located in the 16K space (0000H to 3FFFH).
3.2
PROGRAM MEMORY (ROM): 24448 WORDS x 8 BITS
This is a mask programmable ROM having a configuration of 24448 words x 8 bits to store programs, table data, etc. The program memory is addressed by the program counter. Table data can be referred to by the table reference instruction (MOVT). The branch range enabled by the branch and subroutine call instructions is shown in Fig. 3-2. The entire space branch instruction (BRA !addr1) and the entire space call instruction (CALLA !addr1) allow direct branching to the entire space from 0000H to 5F7FH. The relative branch instruction (BR $addr) enables branch to the [PC contents -15 to -1, +2 to +16] address irrespective of the block boundary. The program memory addresses are 0000H to 5F7FH and the following addresses are especially assigned. (All areas except 0000H and 0001H can be used as the normal program memory.) * Addresses 0000 and 0001H Vector address table for writing the program start address to be set upon RESET input and the RBE and MBE set values. Can be reset and started at any address in a 16K space (0000H to 3FFFH). * Addresses 0002 to 000FH Vector address table for writing the program start address to be set by each vectored interrupt and the RBE and MBE set values. Interrupt service can be started at any address in a 16K space (0000H to 3FFFH). * Addresses 0020 to 007FH Table area to be referred to by GETI instruction*. * GETI instruction is an instruction to realize any 2-byte/3-byte instruction or two 1-byte instructions with one byte. It is used to decrease the number of program bytes. (Refer to 8.1 CHARACTERISTIC INSTRUCTIONS OF PD75237.)
28
PD75237
Fig. 3-2 Program Memory Map
0000H 0002H 0004H 0006H 0008H 000AH 000CH 000EH MBE RBE MBE RBE MBE RBE MBE RBE MBE RBE MBE RBE MBE RBE MBE RBE Internal Reset Start Address (Most Significant 6 Bits) (Least Significant 8 Bits) INTBT/INT4 Start Address INT0 Start Address INT1 Start Address INTCSI0 Start Address INTT0 Start Address INTTPG Start Address INTKS Start Address (Most Significant 6 Bits) (Least Significant 8 Bits) (Most Significant 6 Bits) (Least Significant 8 Bits) (Most Significant 6 Bits) (Least Significant 8 Bits) (Most Significant 6 Bits) (Least Significant 8 Bits) (Most Significant 6 Bits) (Least Significant 8 Bits) (Most Significant 6 Bits) (Least Significant 8 Bits) (Most Significant 6 Bits) (Least Significant 8 Bits) CALLF !faddr Instruction Entry Address BRA !addr1 Instruction Branch Address BRCB !caddr Instruction Branch Address CALLA !addr1 Instruction Branch Address BR $addr1 Instruction Relative Branch Address (-15 to -1 and +2 to +16) BR !addr Instruction Branch Address CALL !addr Instruction Branch Address Branch/call Address by GETI
0020H GETI Instruction Reference Table 007FH 0080H
07FFH 0800H
0FFFH 1000H BRCB !caddr Instruction Branch Address 1FFFH 2000H BRCB !caddr Instruction Branch Address
2FFFH 3000H
BRCB !caddr Instruction Branch Address 3FFFH 4000H BRCB !caddr Instruction Branch Address 4FFFH 5000H BRCB !caddr Instruction Branch Address 5F7FH
Note
As stated above, the interrupt vector start address is 14 bits in length, and should therefore be set in the 16K space (0000H to 3FFFH). In all cases other than those listed above, branch to the address with only the lower 8 bits of the PC changed is enabled by BR PCDE and BR PCXA instructions. 29
Remarks
PD75237
3.3
DATA MEMORY The data memory consists of a static RAM and peripheral hardware. The static RAM incorporates 160 words x 4 bits of memory banks 0, 2 and 3, 768 words x 4 bits of memory bank
1 and 96 words x 4 bits of memory bank 1 which also serves as a display data memory. It is used to store process data and to serve as a stack memory for interrupt execution. General registers, display data memory and various registers of peripheral hardware are mapped at particular addresses of the data memory and such data is manipulated by the general register and memory manipulation instructions. (Refer to Fig. 2-1 Data Memory Configuration and Addressing Range in Each Addressing Mode.) All addresses (000H to 3FFH) of memory banks 0, 1, 2 and 3 can be used as a stack area. Although the data memory consists of one address and 4 bits, it can be manipulated in 8-bit units by the 8-bit memory mainipulation instruction or in bit units by the bit manipulation instruction. Specify an even address by the 8-bit manipulation instruction. The display data memory area (1A0H to 1FFH) is made up as shown in Fig. 3-4. Fig. 3-3 Data Memory Map
Data Memory General Register Area 000H 01FH 020H 256 x 4 0FFH 100H Stack Area Data Area Static RAM (1024 x 4) 19FH Display Data Memory, etc. 1A0H (96 x 4) 1FFH 200H 256 x 4 1 (32 x 4) 0 Memory Bank
256 x 4
2
2FFH 300H
256 x 4
3
3FFH
Not Incorporated F80H Peripheral Hardware Area FFFH 128 x 4 15
30
PD75237
Fig. 3-4 Display Data Memory Configuration
1A1H 1A3H 1A5H 1A7H 1A9H 1ABH 1ADH 1AFH 1B1H 1B3H 1B5H 1B7H 1B9H 1BBH 1BDH 1BFH
1A0H 1A2H 1A4H 1A6H 1A8H 1AAH 1ACH 1AEH 1B0H 1B2H 1B4H 1B6H 1B8H 1BAH 1BCH
1C3H 1C7H 1CBH 1CFH 1D3H 1D7H 1DBH 1DFH 1E3H 1E7H 1EBH 1EFH 1F3H 1F7H 1FBH
1C2H 1C6H 1CAH 1CEH 1D2H 1D6H 1DAH 1DEH 1E2H 1E6H 1EAH 1EEH 1F2H 1F6H 1FAH 1FEH (KS1)
1C1H 1C5H 1C9H 1CDH 1D1H 1D5H 1D9H 1DDH 1E1H 1E5H 1E9H 1EDH 1F1H 1F5H 1F9H 1FDH
1C0H 1C4H 1C8H 1CCH 1D0H 1D4H 1D8H 1DCH 1E0H 1E4H 1E8H 1ECH 1F0H 1F4H 1F8H 1FCH (KS0)
1BEH (KS2) IFFH (PORTH)
No. of manipulatable bits
1 bit
4 bits
8 bits
Remarks 1. 2.
KS0, KS1 and KS2: Key scan register PORTH: High-voltage, high-current output port which also serves as digit output port
31
PD75237
3.4
GENERAL REGISTER: 8 x 4 BITS x 4 BANKS
The general registers are mapped at the special addresses of the data memory. There are 4-bank registers, each bank consisting of eight 4-bit registers (B, C, D, E, H, L, X, A). The register bank (RB) which becomes valid for instruction is given as RB = RBE* RBS (RBS = 0 to 3). Each general register is operated in 4-bit units. BC, DE, HL and XA form register pairs and are used for 8-bit manipulation. In addition to DE and HL, DL also makes up a pair and these three pairs can be used as a data pointer. The general register area can be accessed by address specification as a normal RAM whether or not it is used as a register.
Fig. 3-5 General Register Configuraton
Address 000H 001H 002H 003H 004H 005H 006H 007H 008H
.........
Fig. 3-6 Register Pair Configuration
3 B 3 D 0 3 E 0 H 3 0 X 3 A 3 L 0 0 1 Bank 0 3 C 0 0
3
Data Memory A Register X Register L Register H Register
0
3 Register Bank 0
E Register D Register C Register B Register
Same Configuration as Bank 0
Register Bank 1
00FH 010H
.........
Same Configuration as Bank 0
Register Bank 2
017H 018H
.........
Same Configuration as Bank 0
Register Bank 3
01FH
32
PD75237
3.5
ACCUMULATOR
In the PD75237, A register and XA register pair function as an accumulator. The 4-bit data processing instruction is executed mainly by A register and the 8-bit data processing instruction is executed mainly by XA register pair. For execution of the bit manipulation instruction, the carry flag (CY) functions as a bit accumulator. Fig. 3-7 Accumulator
CY Bit Accumulator
A
4-Bit Accumulator
X
A
8-Bit Accumulator
3.6
STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS) In the PD75237, the static RAM is used as a static memory (LIFO type) and the 8-bit register which holds the
start address information in the stack area is a stack pointer (SP). The stack area is located at addresses 000H to 3FFH of memory banks 0, 1, 2 and 3. Specify one memory bank by a 4-bit SBS. The SP is decremented prior to a write (save) to the stack memory and incremented after a read (restore) from the stack memory. Set SBS by the 4-bit memory manipulation instruction. In this case, set the higher 2-bits to 00. The data to be saved/restored by each stack operation is shown in Figs. 3-9 and 3-10. The SP initial value is set by the 8-bit memory manipulation instruction and the SBS initial value is set by the 4-bit memory manipulation instruction and then the stack area is determined. The SP and SBS contents can also be read. Table 3-1 Stack Areas to be Selected by SBS
SBS Stack Area SBS0 0 1 0 1 Memory bank 0 Memory bank 1 Memory bank 2 Memory bank 3 ------------------------------SBS1 0 0 1 1
When the SP initial value is set to 00H, stack starts with the most significant address (nFFH) of the memory bank (n: n = 0, 1, 2, 3) specified by SBS. The stack area is limited to the memory bank specified by SBS. When stack operation is further carried out at address n00H, the address is reset to nFFH in the same bank. Linear stack past the memory bank boundary is not possible without rewriting SBS. Since RESET input makes the SP and SBS undefined, be sure to initialize the SP and SBS to any desired value at the beginning of the program.
33
PD75237
Fig. 3-8 Stack Bank Select Register Configuration
Address F80H F84H SP7 SP6 SP5 SP4 SP3 SP2 SP1 Fixed to 0 Symbol SP SBS
SBS1 SBS0
000H SBS 0FFH 100H Memory Bank 1 1FFH 200H Memory Bank 2 2FFH 300H Memory Bank 3 3FFH SP SP SP Memory Bank 0 SP
34
PD75237
Fig. 3-9 Data to be Saved into Stack Memory
PUSH Instruction CALL, CALLA and CALLF Instructions Stack SP - 6 SP - 5 SP - 2 SP - 1 SP Lower Half of Register Pair Upper Half of Register Pair SP - 4 SP - 3 SP - 2 SP - 1 SP 0 PC11-PC8 PC14PC13PC12 PC3-PC0 PC7-PC4 MBE RBE * SP - 1 SP SP - 6 SP - 5 SP - 4 SP - 3 SP - 2 0 Interrupt
Stack
Stack PC11-PC8 PC14PC13PC12 PC3-PC0 PC7-PC4 IST1 IST0 MBE RBE PSW CY SK2 SK1 SK0
Fig. 3-10 Data to be Restored from Stack Memory
POP Instruction RET and RETS Instruction RETI Instruction
Stack Lower Half of Register Pair Upper Half of Register Pair SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 0
Stack PC11-PC8 PC14PC13PC12 PC3-PC0 PC7-PC4 MBE RBE * SP + 5 SP + 6 SP SP + 1 SP + 2 SP + 3 SP + 4 0
Stack PC11-PC8 PC14PC13PC12 PC3-PC0 PC7-PC4 IST1 IST0 MBE RBE PSW CY SK2 SK1 SK0
SP SP + 1 SP + 2
*
PSW except MBE and RBE are not saved/restored. means undefined.
Remarks
35
PD75237
3.7
PROGRAM STATUS WORD (PSW): 8 BITS The program status word (PSW) consists of various types of flags closely related to processor operation. The PSW is mapped at addresses FB0H and FB1H in the data memory space and 4 bits at address FB0H can be
operated by the memory manipulation instruction. Normal data memory manipulation instructions cannot be used at address FB1H. Fig. 3-11 Program Status Word Configuration
Address
FB1H
FB0H
Symbol RBE PSW
CY
SK2
SK1
SK0
IST1
IST0
MBE
Non-Manipulatable Manipulatable by a Dedicated Instruction
Manipulatable
Table 3-2 PSW Flag to be Saved/Restored in Stack Operation
Flag to be Saved/Restored During CALL/CALLA/CALLF instruction execution Save Upon hardware interruption During RET/RETS instruction execution Restore During RETI instruction execution All PSW bits restored All PSW bits saved MBE and RBE restored MBE and RBE saved
36
PD75237
Carry flag (CY) The carry flag is a 1-bit flag to store the overflow and underflow generate information when a carry operation instruction (ADDC, SUBC) is executed. It has the bit accumulator function to execute Boolean algebraic operations with the data memory specified by the bit address and to store the result. Carry flag manipulation is carried out using a dedicated instruction irrespective of other PSW bits. When RESET signal is generated, the carry flag becomes undefined. Table 3-3 Carry Flag Manipulation Instructions
Instruction (Mnemonic) SET1 CLR1 NOT1 SKT CY CY CY CY Carry Flag Operation and Processing CY set (1) CY clear (0) CY contents invert SKip if CY contents are 1 CY contents transfer to the specified bit Specified bit contents transfer to CY
(1)
Carry flag manipulation dedicated instruction
Bit transfer instruction
MOV1 mem* .bit CY MOV1 CY, mem* .bit AND1 CY, mem* .bit OR1 CY, mem* .bit XOR1 CY, mem* .bit
Bit Boolean instruction
Specified bit contents ANDed/ORed/XORed with CY contents and the results set to CY
Interrupt service
During interrupt execution Parallel save of other PSW bits and 8 bits to the stack memory --------------------------------------------------------------------------------------------------------------------------------------------------RETI Restore from the stack memory in parallel to other PSW bits
Remarks
mem*.bit indicates the following three bit manipulated addressing operations. * fmem.bit * pmem.@L * @H + mem.bit
(2)
Skip flags (SK2, SK1, SK0) The skip flag is used to store the skipped state and is automatically set/reset when the CPU executes an
instruction. The user cannot directly operate the skip flags as operands.
37
PD75237
(3)
Interrupt status flags (IST1, IST0) The interrupt status flag is a 2-bit flag to store the status of the processing currently being executed. (Refer
to Table 5-3 IST1 and IST0 Interrupt Servicing Statuses for details.) Table 3-4 Interrupt Status Flag Directive Contents
IST1 0 0 1 1
IST0 0 1 0 1
Status of Processing being Executed Status 0 Status 1 Status 2 --
Servicing Contents and Interrupt Control Normal program being executed. All interrupts acknowledgeable. Low or high interrupt being executed. Only high interrupt acknowledgeable. High interrupt being executed. All interrupts non-acknowledgeable. Setting disable
The interrupt priority control circuit (see Fig. 5-1 Interrupt Control Circuit Block Diagram) identifies the interrupt status flag contents and executes multiple interrupt control. If the interrupt is acknowledged, the IST1 and IST0 contents are saved to the stack memory as part of PSW and are automatically changed to the status higher by one level and the values prior to interruption by RETI instruction are restored. The interrupt status flag can be operated by the memory manipulation instruction and the processing status being executed can be changed by program control. Note Before operating this flag, be sure to disable interruption by executing DI instruction and enable interruption by execution EI instruction after operation.
38
PD75237
(4)
Memory bank enable flag (MBE) This is a 1-bit flag to specify the mode to generate the address information of the most significant 4 bits of the 12 bits of the data memory address.
When this flag is set (1), the data memory address space is expanded and all data memory spaces become addressible. When this flag is reset (0), the data memory address space is fixed irrespectively of MBS setting. (See Fig. 2-1 Data Memory Configuration and Addressing Range in Each Addressing Mode.) When RESET input is applied, the bit 7 contents at address 0 of the program memory are set and the MBE is automatically initialized. In vectored interrupt service, the bit 7 contents of the corresponding vector address table are set and the MBE status in the interrupt service is automatically set. Normally, set MBE = 0 for interrupt service and use the static RAM of memory bank 0. (5) Register bank enable flag (RBE) This is a 1-bit flag to determine whether or not the general register bank configuration should be expanded. When this flag is set (1), one general register can be selected from register banks 0 to 3 depending on the
register bank select register (RBS) contents. When this flag is reset (0), register bank 0 is selected as a general register irrespective of the register bank select register (RBS) contents. Upon RESET input, the bit 6 contents at address 0 of the program memory are set and the flag is automatically initialized. When a vectored interrupt is generated, the bit 6 contents of the corresponding vector address table are set and the RBE status in interrupt service is automatically set. Normally, set RBE = 0 for interrupt service. Use register bank 0 for 4-bit operation and register banks 0 and 1 for 8-bit operation.
39
PD75237
3.8
BANK SELECT REGISTER (BS)
The bank select register (BS) consists of a register bank select register (RBS) and a memory bank select register (MBS). The RBS and MBS are used to specify the register bank and the memory bank to be used, respectively. The RBS and MBS are set by SEL RBn and SEL MBn instructions, respectively. The BS can be saved/restored the stack area in 8-bit units by PUSH BS/POP BS instruction. Fig. 3-12 Bank Select Register Configuration
Address
MBS
RBS
Symbol BS
F82H
MBS3 MBS2 MBS1 MBS0
0
0
RBS1 RBS0
(1)
Memory bank select register (MBS) The memory bank select register in a 4-bit register to store the most significant 4-bit address information of the data memory address (12 bits) and the memory bank to be accessed is specified by the MBS contents. Banks 0, 1, 2, 3 and 15 can be specified. The MBS is set by SEL MBn instruction. (n = 0, 1, 2, 3, 15) The address range for MBE and MBS setting is shown in Fig. 2-1. Upon RESET input, the MBS is initialized to "0".
(2)
Register bank select register (RBS) The register bank select register is used to specify the register bank for use as a general register and can set banks 0 to 3. The RBS is set by SEL RBn instruction. (n = 0 to 3) Upon RESET input, the RBS is initialized to "0". Table 3-5 RBE, RBS and Register Banks to be Selected
RBS RBE 3 0 0 2 0 1 x 0 0 1 0 0 1 1 0 1 Bank 2 selected Bank 3 selected 0 x 0 1 Fixed to bank 0 Bank 0 selected Bank 1 selected Register Bank
Fixed to 0
Remarks
x : Don't care
40
PD75237
4. PERIPHERAL HARDWARE FUNCTIONS
4.1 DIGITAL INPUT/OUTPUT PORTS The PD75237 employs the memory mapped I/O and all input/output ports are mapped in the data memory space. Fig. 4-1 Digital Port Data Memory Address
Address FF0H FF1H FF2H FF3H FF4H FF5H FF6H FF7H FF8H FF9H FFAH FFBH FFCH FFDH FFEH FFFH 3 P03 P13 P23 P33 P43 P53 P63 P73 P83 P93 P103 P113 P123 P133 P143 P153 2 P02 P12 P22 P32 P42 P52 P62 P72 P82 P92 P102 P112 P122 P132 P142 P152 1 P01 P11 P21 P31 P41 P51 P61 P71 P81 P91 P101 P111 P121 P131 P141 P151 0 P00 P10 P20 P30 P40 P50 P60 P70 P80 P90 P100 P110 P120 P130 P140 P150
Symbol
PORT0 PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORT7 PORT8 PORT9 PORT10 PORT11 PORT12 PORT13 PORT14 PORT15
41
PD75237
(1) Digital input/output port configuration The digital input/output port configurations are shown in Figs. 4-2 to 4-11. (2) Input/output mode setting The input/output mode of each input/output port is set by the port mode register as shown in Fig. 4-12. Each port acts as an input when the corresponding port mode register bit is "0" and as an output port when the bit is "1". Port mode register groups A and B each are set by the 8-bit memory manipulation instruction. Upon RESET input, all bits of each port mode register are cleared to "0". Thus, the output buffer is turned OFF and all the ports are set to the input mode. (3) Digital input/output port operation The operations of the port and pin for instruction execution vary, depending on the input/output mode setting as shown in Table 4-1. Table 4-1 Input/Output Port Operations for Input/Output Instruction Execution
Input Mode (Corresponding Bit 0 of Mode Register) [Output Buffer OFF] When 1-bit test instruction, 1-bit input instruction, 4-bit or 8-bit instruction is executed When 4-bit or 8-bit output instruction is executed
Output Mode (Corresponding Bit 1 of Mode Register) [Output Buffer ON]
Each pin data input
Output latch contents input
Accumulator data transfer to output latch Output latch contents become undefined
Accumulator data output to output pin Output pin status change according to instruction
When 1-bit output instruction* is executed
*
SET1/CLR1/MOV1 PORTn.bit, CY, etc.
42
PD75237
Fig. 4-2 Configurations of Port 0, 1 and 8
Internal SCK0
SI0 SCK0 INT4
SO0
P01 Output Latch
VDD
CSIM0
Selector
Selector
8
Pull-Up Resistor
Bit 0 of POGA
P-ch
P00/INT4 P01/ SCK0 P02/SO0/SB0 P03/SI0/SB1
Input Buffer Output buffer capable of switching between push-pull output and N-ch open drain output Pull-Up Resistor
VDD
P-ch
Bit 1 of POGA
Internal Bus
Input Buffer
o or fX/64
Noise Eliminator
P10/INT0 P11/INT1 P12/INT2 P13/TI0
TI0 INT2INT1 INT0
Input buffer having hysteresis characteristics Internal
SI1 SO1 SCK1
SCK1
PPO
8
CSIM1
P80/PPO P81/ SCK1 P82/SO1 P83/SI1
Input Buffer
43
PD75237
Fig. 4-3 Port 3n and Port 6n Configurations (n = 0 to 3)
VDD
Input Buffer
PMm n=0 M P X PMm n=1
Bit m of POGA Output Buffer Pull-Up Resistor
P-ch
Internal Bus
Output Latch
Pm n
PMm n
Corresponding Bit of Port Mode Register Group A m = 3, 6 n = 0 to 3
(
)
Fig. 4-4 Port 2 Configuration
VDD
Pull-Up Resistor P-ch Bit m of POGA Input Buffer PMm=0 M P X
PMm=1
Internal Bus
Pm0 Pm1 Pm2 Pm3 Output Buffer PMm Corresponding Bit of Port Mode Register Group B (m = 2)
Output Latch
44
PD75237
Fig. 4-5 Configurations of Ports 4 and 5
VDD
Input Buffer PMm=0
Pull-Up Resistor Mask Option
M P X PMm=1
Internal Bus
Pm0 Pm1 Pm2 Pm3 N-ch Open Drain Output Buffer PMm Corresponding Bit of Port Mode Register Group B (m = 4, 5)
Output Latch
45
PD75237
Fig. 4-6 Port 7 Configuration
Input Buffer
PMm=0
M P X PMm=1
Internal Bus
Pm0
Output Latch
Pm1 Pm2 Pm3
Output Buffer
PMm
Mask Option Pull-Down Resistor
Corresponding Bit of Port Mode Register Group B (m = 7)
Fig. 4-7 Port 9 Configuration
Input Instruction
Input Buffer
P90/AN4
Internal Bus
P91/AN5 P92/AN6 P93/AN7
To A/D Converter
46
PD75237
Fig. 4-8 Configurations of Ports 10 and 11
SK P-ch Open Drain Output Buffer SK+1 /Pm1 SK /Pm0
SK+1
SK+2
SK+2 /Pm2
SK+3 Internal Bus
SK+3 /Pm3
Mask Option
Pull-Down Resistor 4 DSPM Mask Option VLOAD (Simultaneously specified for S16 to S23) 8 STATB
Remarks
1. 2.
Port 10: K = 16, m = 10 Port 11: K = 20, m = 11
Fig. 4-9 Configurations of Ports 12 and 13
SK P-ch Open Drain Output Buffer SK+1 /Pm1
SK /Pm0
SK+1
SK+2
SK+2 /Pm2
SK+3 Internal Bus
SK+3 /Pm3
Mask Option
Pull-Down Resistor 4 DSPM VLOAD
8
STATA
Remarks
1. 2.
Port 12: K = 0, m = 12 Port 13: K = 4, m = 13
47
PD75237
Fig. 4-10 Port 14 Configuration
P-ch Open Drain Output Buffer Output Buffer
S8/P140 M S9/P141 P X
*
S8
Internal Bus
S9 S10 S11
S10/T15/P142
*
S11/T14/P143
4
DSPM.3
S15 S14
Mask Option (for Each Pin) Pull-Down Resistor
8 4
STATA DIGS
VLOAD
*
Selector
Fig. 4-11 Configurations of Ports 15 and H
P-ch Open Drain Output Buffer Output Buffer *
S12/T13/P150/PH0
M P
* * * *
S13/T12/P151/PH1
S12
Internal Bus
S13 S14 S15
*
X
*
S14/T11/P152/PH2
*
S15/T10/P153/PH3
Mask Option (for Each Pin) Pull-Down Resistor
PH1PH3 PH0PH2 4 DSPM.3
T12T10 T13T11
8 4
STATA VLOAD DIGS
*
Selector
48
PD75237
Fig. 4-12 Port Mode Register Format Port mode register group A
Address FE8H 7 PM63 6 PM62 5 PM61 4 PM60 3 PM33 2 PM32 1 PM31 0 PM30 Symbol PMGA
Symbol PM3n, PM6n PMGA 0 1
P3n and P6n Pin Input/Output Specification (n = 0 to 3) Input mode (output buffer OFF) Output mode (output buffer ON)
Port mode register group B
Address FECH 7 PM7 6 5 PM5 4 PM4 3 2 PM2 1 0 Symbol PMGB
Symbol PMn PMGB 0 1
Port n Input/Output Specification (n = 2, 4, 5, 7) Input mode (output buffer OFF) Output mode (output buffer ON)
Remarks
---- : 0 or 1
(4) Pull-up resistor register group A (POGA) Pull-up resistor register group A is intended to specify pull-up resistors to be built in ports 0 to 3 and port 6 (except P00). Fig. 4-13 shows the format. Set "1" when a pull-up resistor is incorporated or "0" when it is not incorporated. Fig. 4-13 Pull-Up Resistor Register Group A Format
Address FDCH 7 6 PO6 5 4 3 PO3 2 PO2 1 PO1 0 PO0 Symbol POGA
Port 0 (P01 to P03) Port 1 (P10 to P13) Port 2 (P20 to P23) Port 3 (P30 to P33) Port 6 (P60 to P63)
Note
Mask option by which pull-up resistors at ports 4 and 5 and pull-down resistors at port 7 and ports 10 to 15 can be incorporated bit-wise.
Remarks
---- : 0 or 1
49
PD75237
4.2
CLOCK GENERATOR (1) Clock generator configuration The clock generator is a circuit to generate clocks to be supplied to the CPU and the peripheral hardware. Its configuration is shown in Fig. 4-14. Fig. 4-14 Clock Generator Block Diagram
XT1
Subsystem Clock Generator * FIP Controller/Driver * Basic Interval Timer * Timer/Event Counter * Serial Interface * Watch Timer * Clock Output Circuit * INT0 Noise Eliminator
f XT
Watch Timer Timer/Pulse Generator
XT2 X1
X2
Mainsystem Clock Generator
fX 1/ 1/ 1/ 2 4 16
1/8~1/4096 Frequency Divider
SCC SCC3 SCC0
Internal Bus
Oscillation Stop
Selector
Selector
Frequency Divider
1/4
PCC PCC0
* CPU * INT0 Noise Eliminator * Clock Output Circuit
PCC1 4 HALT F/F HALT * STOP * PCC2 PCC3 R Q S
PCC2 and PCC3 Clear
STOP F/F Q S
Wait Release Signal from BT RESET Signal
R
*
Instruction execution 1. 2. 3. 4. 5. 6. fX = Main system clock frequency fXT = Subsystem clock frequency = CPU clock
Standby Release Signal from Interrupt Control Circuit
Remarks
5
50
PCC: Processor clock control register SCC: System clock control register 1 clock cycle (tCY) of is 1 machine cycle of an instruction. For tCY, see "AC Characteristics" in 11. ELECTRICAL SPECIFICATIONS.
PD75237
(2) Clock generator functions The clock generator generates the following clocks and controls the CPU operating modes including the standby mode. * Main system clock : fX * Subsystem clock : fXT * CUP CLOCK : * Clocks for peripheral hardware The following clock generator operations are determined by the processor clock control register (PCC) and the system clock control register (SCC): (a) Upon RESET input, the lowest speed mode (10.7 s : at 6.0 MHz operation)*1 of the main system clock is selected. (PCC = 0, SCC = 0) (b) One of the four-level CPU clocks can be selected by setting the PCC with the main system clock selected. (0.67 s, 1.33 s, 2.67 s, 10.7 s : at 6.0 MHz operation)*2 (c) Two standby modes, the STOP and HALT modes, are available with the main system clock selected.
(d) The clock generator can be operated at an ultra-low speed and with low-level power consumption (122 s : at 32.768 KHz operation) by selecting the subsystem clock with SCC. (e) Main system clock oscilloation can be stopped by SCC with the subsystem clock selected. The HALT mode can also be used but the STOP mode cannot be used. (Subsystem clock oscillation cannot be stopped.) (f) Divided system clocks are supplied to the peripheral hardware. Subsystem clocks can be directly supplied to the watch timer to that the timer function can be continued. (g) When the subsystem clock is selected, the watch timer can operate normally. However, other hardware cannot be used if the main system clock is stopped. * 1. 2. 15.3 s : at 4.19 MHz operation 0.95 s, 1.91 s, 3.82 s, 15.3 s : at 4.19 MHz operation
51
PD75237
(3) Processor clock control register (PCC) The PCC is a 4-bit register to select the CPU clock with the lower 2 bits and to control the CPU operating mode with the higher 2 bits. (See Fig. 4-15 Processor Clock Control Register Format.) When bit 3 or 2 is set (1), the standby mode is set. If the standby mode is released by the standby release signal, both bits are automatically cleared and the normal operating mode is set. (For details, refer to 6. STANDBY FUNCTIONS.) The lower 2 bits of the PCC are set by the 4-bit memory manipulation instruction (with the higher 2 bits set to "0"). Bits 3 and 2 are reset "1" by the STOP and HALT instructions, respectively. The STOP and HALT instructions can always be executed irrespective of the MBE contents. The CPU clock selection is possible only when operated on the main system clock. When operated on the subsystem clock, the lower 2 bits of PCC are invalidated and fXT/4 is set. The STOP instruction is also enabled only when in operation with the main system clock. RESET input clears PCC to "0".
52
PD75237
Fig. 4-15 Processor Clock Control Register Format
Address 3 FB3H PCC3 2 PCC2 1 PCC1 0 PCC0 PCC Symbol
CPU Clock Select Bit (When fX = 6.0 MHz)
SCC = 0 SCC = 1 Values in parentheses are when fx = 6.0 MHz Values in parentheses are when fXT = 32.768 kHz CPU Clock Frequency 0 0 1 Machine Cycle 10.7 s CPU Clock Frequency 1 Machine Cycle 122 s
= fX/64 (93.7 kHz) = fX/16 (375 kHz) = fX/8 (750 kHz) = fX/4 (1.5 MHz)
= fXT/4 (8.192 kHz)
0
1
2.67 s
Setting prohibited
1
0
1.33 s
= fXT/4 (8.192 kHz)
122 s
1
1
0.67 s
(When fX = 4.19 MHz)
SCC = 0 Values in parentheses are when fx = 4.19 MHz CPU Clock Frequency 0 0 1 Machine Cycle 15.3 s SCC = 1 Values in parentheses are when fXT = 32.768 kHz CPU Clock Frequency 1 Machine Cycle 122 s
= fX/64 (65.5 kHz) = fX/16 (262 kHz) = fX/8 (524 kHz) = fX/4 (1.05 MHz)
= fXT/4 (8.192 kHz)
0
1
3.81 s
Setting prohibited
1
0
1.91 s
= fXT/4 (8.192 kHz)
122 s
1
1
0.95 s
Remarks
1. 2.
fX : Main system clock oscillator output frequency fXT : Subsystem clock oscillator output frequency
CPU Operating Mode Control Bit
0 0 1 1 0 1 0 1 Normal operating mode HALT mode STOP mode Setting prohibited
53
PD75237
(4) System clock control register (SCC) The SCC is a 4-bit register to select the CPU clock with the least significant bit and to control main system clock oscillation stop with the most significant bit (refer to Fig. 4-16). Although SCC.0 and SCC.3 are located at the same data memory address, both bits cannot be changed simultaneously. Thus, SCC.0 and SCC.3 are set by the bit manipulation instruction. SCC.0 and SCC.3 can always be bit manipulated irrespective of the MBE contents. Main system clock oscillation can be stopped by setting SCC.3 only when in operation with the subsystem clock. Oscillation when in operation with the main system clock is stopped by the STOP instruction. RESET input clears SCC to "0". Fig. 4-16 System Clock Control Register Format
Address 3 FB7H SCC3 2 1 0 SCC0
Symbol SCC
SCC3 0 0 1 1
SCC0 0 1 0 1
System Clock Selection Main system clock
Main System Clock Oscillation Oscillation enabled
Subsystem clock Setting prohibited Subsystem clock Oscillation stop
Note
1. A maximum of 1/fXT is required to change the system clock. Thus, when stopping the main system clock oscillation, change the clock to the subsystem clock and set SCC.3 following the passage of more than the machine cycles described in Table 4-2. 2. The normal STOP mode cannot be set if oscillation is stopped by setting SCC.3 while in operation with the main system clock. 3. If SCC.3 is set to "1", X1 input is internally short-circuited to VSS (GND potential) to suppress crystal oscillator leakage. Thus, when using an external clock for the main system clock do not set SCC.3 to "1". 4. When PCC = 0001B ( = fX/16 selected), do not set SCC.0 to "1". When switching from the main system clock to the subsystem clock, do so after setting PCC to another value (PCC 0001B). Do not set PCC = 0001B while in operation with the subsystem clock.
54
PD75237
(5) System clock oscillator The main system clock oscillator oscillates with a crystal resonator (with a standard frequency of 6.0 MHz) or a ceramic resonator connected to the X1 and X2 pins. External clocks can be input to this oscillator. Fig. 4-17 External Circuit of Main System Clock Oscillator (a) Crystal/ceramic Oscillation
PD75237
X1
(b) External clock
PD75237
External Clock
X1
X2
X2
Crystal or Ceramic Resonator
Note
The STOP mode cannot be set while an external clock is input because the X1 pin is short-circuited to VSS in the STOP mode. The subsystem clock oscillator oscillates with a crystal resonator (with a standard frequency of 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to this oscillator. Fig. 4-18 External Circuit of Subsystem Clock Oscillator (a) Crystal oscillation
PD75237
XT1 32.768 kHz
(b) External clock
PD75237
External Clock
XT1
Leave open
XT2
XT2
Note
When using a main system clock and subsystem clock oscillator, wire the crosshatched section in Figs. 4-17 and 4-18 as follows to prevent any effect of the wiring capacity. * Make the wiring as short as possible. * Do not allow wiring to intersect with other signal conductors. Do not allow wiring to be near a line through which varying high current flows. * Set the oscillator capacitor grounding point to the same potential as that of VSS. Do not ground to a ground pattern through which high current flows. * Do not fetch signals from the oscillator. The subsystem clock oscillator has a low amplification factor to maintain low current consumption and is more likely to malfunciton due to noise than the main system clock oscillator. Thus, take extra care when using a subsystem clock. 55
PD75237
(6) Time required for system clock and CPU clock switching The system clock and the CPU clock can be switched to each other with the least significant bit of the SCC and the lower 2 bits of the PCC. This switching is not executed just after register rewrite and operation continues with the previous clock during the specified machine cycle. Thus, to stop main system clock oscillation, it is necessary to execute the STOP instruction or to set SCC.3 after the specified switching time. Table 4-2 Maximum Time Required for System Clock and CPU Clock Switching
Set Value before Switching SCC 0 PCC 1 0 PCC 0 0
Set Value after Switching SCC0 PCC1 PCC0 SCC0 PCC1 PCC0 SCC0 PCC1 PCC0 SCC0 PCC1 PCC0 SCC0 PCC1 PCC0 0 0 0 0 0 1 0 1 0 0 1 1 1 x x fX machine cycle 64fXT (3 machine cycle) Setting prohibited
1 machine cycle
1 machine cycle
1 machine cycle
0 0 1
1
4 machine cycle
4 machine cycle
4 machine cycle
0
8 machine cycle
8 machine cycle
8 machine cycle
fX machine cycle 8fXT (23 machine cycle) fX machine cycle 4fXT (64 machine cycle)
1
1
16 machine cycle
16 machine cycle
16 machine cycle
1
x
x
1 machine cycle
Setting prohibited
1 machine cycle
1 machine cycle
Remarks
1. 2.
CPU clock is a clock to be supplied to the internal CPU of PD75237 and its inverse number is the minimum instruction time (defined as "one machine cycle" in this manual). Values in parentheses are when fX = 6.0 MHz and fXT = 32.768 kHz.
Note
When PCC = 0001B ( = fX/16 selected), do not set SCC.0 to "1". When switching from the main system clock to the subsystem clock, do so after setting PCC to another value (PCC 0001B). Do not set PCC = 0001B while in operation with the subsystem clock.
56
PD75237
(7) System clock and CPU clock switching procedure System clock and CPU clock switching is described referring to Fig. 4-19. Fig. 4-19 System Clock and CPU Clock Switching
ON Commercial Power Supply OFF
VDD Pin Voltage
RES Signal Wait 21.8 ms [31.3 ms] System Clock CPU Clock
fX
10.7 s [15.3 s]
fX
0.67 s [0.95 s]
fXT
122 s
fX
0.67 s [0.95 s]
Internal Reset Operation
Remarks
fX=6.0 MHz ( fXT=32.768 kHz ) , values in brackets are when fX = 4.19 MHz.
RESET input starts the CPU at the lowest speed (21.8 ms : at 6.0 MHz operation)*1 of the main system clock after the wait time (10.7 s : at 6.0 MHz operation)*2 for maintaining the oscillation stabilize time. The CPU rewrites the PCC and operates at its maximum available speed after the lapse of sufficient time for the VDD pin voltage to increase to a voltage allowing the highest speed operation. The CPU detects commercial power-off from the interrupt input (INT4 is effective), sets SCC.0 and operates with the subsystem clock. (At this time, subsystem clock oscillation must have started beforehand. ) After the passage of time required for the CPU clock to switch to the subsystem clock (32 machine cycles), the CPU sets SCC.3 to stop main system clock oscillation. 4 After the CPU detects the commercial power restored from the interrupt, it clears SCC.3 and starts main system clock oscillation. Following the passage of time required for oscillation stabilization, the CPU clears SCC.0 and operates at its highest speed. * 1. 2. 31.3 ms at 4.19 MHz operation 15.3 s at 4.19 MHz operation
57
PD75237
4.3
CLOCK OUTPUT CIRCUIT (1) Clock output circuit configuration The clock output circuit is configured as shown in Fig. 4-20. (2) Clock output circuit functions The clock output circuit is intended to generate clock pulses from the P22/PCL pin. It is used for remotecontrolled output or clock pulse supply to the peripheral LSI. Follow the procedure below to generate clock pulses. (a) Select the clock output frequency. Do not output clocks. (b) Write 0 to P22 output latch. (c) Set the port 2 input/output mode to `output'. (d) Enable clock output. Fig. 4-20 Clock Output Circuit Configuration
From Clock Generator
f x /23 f x /24 f x /2
6
Output Buffer Selector
PCL/P22
PORT2.2 CLOM 3 0 CLOM CLOM CLOM 1 0
P22 Output Latch
PMGB Bit 2
Port 2 Input/ Output Mode Specification Bit
4
Internal Bus
Remarks
The clock output circuit has such a configuration as to prevent pulses having short widths when switching clock output enable/disable.
58
PD75237
(3) Clock output mode register (CLOM) The CLOM is a 4-bit register to control clock output. The CLOM is set by a 4-bit memory manipulation instruction. Data cannot be read from the CLOM. Example CPU clock output from PCL/P22 pin SEL MB15 ; Or CLR1 MBE MOV A, #1000B MOV CLOM, A
RESET input clears the CLOM to 0 and disables clock output. Fig. 4-21 Clock Output Mode Register Format
Address 3 FD0H CLOM3 2 0 1 0 CLOM Symbol CLOM 1 CLOM0
Clock Output Frequency Select Bit (When fX = 6.0 MHz)
0 0 1 1 0 1 0 1
output* (1.50 MHz, 750 kHz, 375 kHz, 93.7 kHz)
fX/23 output (750 kHz) fX/24 output (375 kHz) fX/26 output (93.7 kHz)
(When fX = 4.19 MHz)
0 0 1 1 0 1 0 1
output* (1.05 MHz, 524 kHz, 262 kHz, 65.5 kHz)
fX/23 output (524 kHz) fX/24 output (262 kHz) fX/26 output (65.5 kHz)
* is a CPU clock to be selected by PCC.
Clock Output Enable/Disable Bit
0 1 Output disabled Output enabled
Note
Be sure to write "0" to bit 2 of CLOM.
59
PD75237
(4) Example of application to remote-controlled output The clock output function of the PD75237 can be applied to remote-controlled output. The carrier frequency of remote-controlled output is selected by the clock frequency select bit of the clock output mode register. Pulse output is enabled/disabled by controlling the clock output enable/disable bit by software. The clock output circuit has such a configuration as to prevent pulses having short widths when switching clock output enable/disable. Fig. 4-22 Remote-Controlled Output Application Example
CLOM.3
PCL Pin Output
60
PD75237
4.4
BASIC INTERVAL TIMER (1) Basic interval timer configuration The basic interval timer configuration is shown in Fig. 4-23. (2) Basic interval timer functions The basic interval timer has the following functions: (a) Interval timer operation to generate reference time (at any of four time intervals) (b) Watchdog timer application to detect inadvertent program loop (c) Wait time select and count upon standby mode release (d) Count contents read Fig. 4-23 Basic Interval Timer Configuration
From Clock Generator
Clear
Clear
f x /25 f x /27 MPX f x /2
9
Basic Interval Timer (8-Bit Freqency Divider)
Set
BT Interrupt Request Flag
f x /212
BT
IRQBT
Vectored Interrupt Request Signal
3
Wait Release Signal upon Standby Mode Release
BTM3
BTM2
BTM1
BTM0
BTM 8
SET1*
4
Internal Bus
*
Instruction execution
61
PD75237
(3) Basic interval timer mode register (BTM) The BTM is a 4-bit register to control basic interval timer operations. The BTM is set by a 4-bit memory manipulation instruction. Bit 3 can be set independently by a bit manipulation instruction. When bit 3 is set "1", the basic interval timer contents and the basic interval timer interrupt request flag (IRQBT) are simultaneously cleared (basic interval timer start). RESET input clears the contents to "0" and sets the interrupt request signal generation interval time to its maximum value. Fig. 4-24 Basic Interval Timer Mode Register Format
Address 3 F85H BTM3 2 BTM2 1 BTM1 0 BTM0 BTM Symbol
(When fX = 6.0 MHz)
Input Clock Specification 0 0 1 1 0 1 0 1 0 1 1 1 fX/212 (1.46 kHz) fX/29 (11.7 kHz) fX/27 (46.9 kHz) fX/25 (188 kHz) Setting prohibited Interrupt Interval Time (Wait time upon standby mode release) 220/fX (175 ms) 217/fX (21.8 ms) 215/fX (5.46 ms) 213/fX (1.37 ms)
In all other cases
(When fX = 4.19 MHz)
Input Clock Specification 0 0 1 1 0 1 0 1 0 1 1 1 fX/212 (1.02 kHz) fX/29 (8.18 kHz) fX/27 (32.768 kHz) fX/25 (131 kHz) Setting prohibited Interrupt Interval Time (Wait time upon standby mode release) 220/fX (250 ms) 217/fX (31.3 ms) 215/fX (7.82 ms) 213/fX (1.95 ms)
In all other cases
Basic Interval Timer Start Control Bit
The basic interval timer is started (counter and interrupt request flag clear) by writing "1". When the timer starts operating, it is automatically reset to "0".
62
PD75237
(4) Basic interval timer operation The basic interval timer (BT) is always incremented by clocks from the clock generator and sets the interrupt request flag (IRQBT) due to an overflow. BT count operation cannot be stopped. Four interrupt generate intervals are available by setting the BTM (refer to Fig. 4-24 Basic Interval Timer Mode Register Format). The basic interval timer and the interrupt request flag can be cleared by setting bit 3 of the BTM (1) (interval timer start instruction). The count state can be read from the basic interval timer (BT) by the 8-bit manipulation instruction. Data cannot be written to the BT. Note When reading the basic interval timer count contents, execute the read instruction twice and compare the two read contents so as not to read unstable data undergoing count update. If the two values are both acceptable, use the second read value as the correct one. If they differ completely, execute reading again from the beginning. To obtain the oscillation stabilize time from STOP mode release to system clock oscillation stabilization, the wait function is available to stop CPU operation until the basic interval timer overflows. Wait time after RESET input is fixed, however, if the STOP mode has been released by interrupt generation, the wait time can be selected by BTM setting. In that case, the wait time is equal to the interval time shown in Fig. 4-24. BTM setting must be done before STOP mode setting. (For details, refer to 6 . STANDBY FUNCTIONS.) 4.5 TIMER/EVENT COUNTER (1) Timer/event counter functions The timer/event counter has the following functions. (a) (b) (c) (d) Program interval timer operation Output of square wave with any frequency to PTO0 pin Event counter operation Output of N-divided TI0 pin input to PTO0 pin (frequency divider operation)
(e) Serial shift clock supply to the serial interface circuit (f) Count state read function
63
64 Fig. 4-25 Timer/Event Counter Block Diagram
Internal Bus
8
SET1*1
TM0 --
8
8
TMOD0
TOE0
TO Enable Flag
PORT2.0
P20 Output Latch
PGMB Bit 2
Port 2 Input /Output Mode
TM07TM06 TM05 TM04 TM03TM02 --
Modulo Register (8)
PORT1.3
8
Match Comparator (8)
To Serial Interface
TOUT F/F
Reset Output Buffer
Input Buffer *2 P13/TI0 From Clock Generator Event Counter #1 (Refer to Fig. 4-26)
P20/PTO0
8 T0
Count Register (8)
MPX
CP
Clear Timer Operation Start
(
INTT0 IRQT0 Set Signal
)
RESET IRQT0 IRQT0 Clear Signal
* 1. 2.
Instruction execution P13/TI0 pin is an external event pulse input pin which serves as timer/event counter and event counter.
PD75237
PD75237
(2) Timer/event counter mode register (TMO) and timer/event counter output enable flag (TOE0) The timer/event counter mode register (TM0) is an 8-bit register to control the timer/event counter and is set by an 8-bit memory manipulation instruction. Fig. 4-27 shows the timer/event counter mode register format. Bit 3 is a timer start command bit which can be set independently. When the timer starts operating, this bit is automatically reset to "0". RESET input clears all bits of the TM0 to 0. The timer/event counter output enable flag (TOE0) controls enable/disable for output to the PTO0 pin in the timer out F/F (TOUT F/F) state. Fig. 4-26 shows the timer/event counter output enable flag format. The timer out F/F (TOUT F/F) is an F/F which is reversed by a match signal transmitted from the comparator. The timer out F/F is reset by an instruction which sets bit 3 of the TM0. RESET input clears TOE0 and TOUT F/F to 0. Fig. 4-26 Timer/Event Counter Output Enable Flag Format
3 TOE0
Address FA2H
Timer/Event Counter Output Enable Flag
0 1 Disabled Enabled
65
PD75237
Fig. 4-27 Timer/Event Counter Mode Register Format
Address FA0H 7 6 TM06 5 TM05 4 TM04 3 TM03 2 TM02 1 0 Symbol TM0
Operating Mode
Count operation 0 Stop (with count contents held) Count operation
1
Timer Start Command Bit
Writing "1" clears the counter and IRQT0 flag. If bit 2 has been set to "1", the counter operation starts.
Count Pulse (CP) Select Bit (When fX = 6.0 MHz)
TM06 0 0 1 1 1 1 TM05 0 0 0 0 1 1 In all other cases TM04 0 1 0 1 0 1 Count Pulse (CP) TI0 input rising edge TI0 input falling edge fX/210 (5.86 kHz) fX/28 (23.4 kHz) fX/26 (93.8 kHz) fX/24 (375 kHz) Setting prohibited
(When fX = 4.19 MHz)
TM06 0 0 1 1 1 1 TM05 0 0 0 0 1 1 In all other cases TM04 0 1 0 1 0 1 Count Pulse (CP) TI0 input rising edge TI0 input falling edge fX/210 (4.09 kHz) fX/28 (16.4 kHz) fX/26 (65.5 kHz) fX/24 (262 kHz) Setting prohibited
66
PD75237
(3) Timer/event counter operating modes The count operation stop mode and the count operating mode are available by setting the mode register for the timer/event counter operation. The following operations are enabled irrespective of the mode register setting: (a) (b) (c) (d) TI0 pin signal input and test (Dual-function pin P13 input testable) Output of the timer out F/F state to PTO0 Modulo register (TMOD0) setting Count register (T0) read
(e) Interrupt request flag (IRQT0) set/clear/test (a) Count operation stop mode When TM0 bit 2 is 0, this mode is set. In this mode, count operation is not carried out because count pulse (CP) supply to the count register is stopped. (b) Count operating mode When TM0 bit 2 is 1, this mode is set. The count pulse selected by bits 4 to 6 is supplied to the count register and the count operation shown in Fig. 4-28 is carried out. The timer operation is normally started by the following operations in the described order. Set the number of counts to the modulo register (TMOD0). Set the operating mode, count clock and start command to the mode register (TM0). Set the modulo register by an 8-bit data transfer instruction. Fig. 4-28 Operation in Count Operating Mode
TI0 CP Count Register (T0)
INTT0 (IRQT0 Set Signal)
Internal Clock
{
MPX
Clear
Comparator Match
TOUT F/F
PTO0
Modulo Register (TMOD0) To Serial Interface (Channel 0)
67
PD75237
(4) Timer/event counter time setting [Timer set time] (cycle) is obtained by dividing [Modulo register contents + 1] by [Count pulse frequency] selected by timer mode register setting. T (sec) = n+1 fCP = (n + 1) * (Resolution)
T (sec) : Timer set time (sec) fCP (Hz) : Count pulse frequency (Hz) n : Modulo register value (n 0)
Once the timer is set, an interrupt request signal (IRQT0) is generated at the set intervals. Table 4-3 shows the resolutions with each count pulse of the timer/event counter and the maximum set time (with FFH set to the modulo register). Table 4-3 Resolution and Maximum Set Time (When fX = 6.0 MHz)
Mode Register TM06 TM05 TM04 1 1 1 1 0 0 1 1 0 1 0 1 Timer Channel 0 Resolution 171 s 42.7 s 10.7 s 2.67 s Maximum Set Time 43.7 ms 10.9 ms 2.73 ms 683 s
(When fX = 4.19 MHz)
Mode Register TM06 TM05 TM04 1 1 1 1 0 0 1 1 0 1 0 1 Timer Channel 0 Resolution 244 s 61.1 s 15.3 s 3.81 s Maximum Set Time 62.5 ms 15.6 ms 3.91 ms 977 s
68
PD75237
4.6 (1)
WATCH TIMER Watch timer The PD75237 incorporates one channel of watch timer having a configuration shown in Fig. 4-29.
(2)
Watch timer functions (a) Sets the test flag (IRQW) at 0.5-sec intervals. The standby mode can be released by IRQW. (b) (c) (d) (e) 0.5-second interval can be set with the main system clock (4.19 MHz) or subsystem clock (32.768 kHz). The fast mode enables to set 128-time (3.91 ms) interval useful to program debugging and inspection. The fixed frequencies (2.048 kHz, 4.096 kHz and 32.768 kHz) can be output to the P23/ BUZ pin for use to generate buzzer sound and trim the system clock oscillator frequency. Since the frequency divider can be cleared, the watch can be started from zero second.
Fig. 4-29 Watch Timer Block Diagram
fW (256 Hz : 3.91 ms) 27 fX 128
From Clock Generator
(32.768 kHz)
fXT (32.768 kHz)
Selector
fW (32.768 kHz) fW 8 fW 16
Frequency Divider
(4.096 kHz)
fW 214
Selector
(
INTW IRQW
Set Signal
)
( 2 Hzsec 0.5 )
Output Buffer
P23/BUZ
Clear Selector
WM WM7 0 WM5 WM4 0 WM2 WM1 WM0
PORT2.3
Bit 2 of PMGB Port 2 Input/ Output Mode
P23 Output Latch
8
Internal Bus
Remarks Note
Values at fX = 4.194304 MHz and fXT = 32.768 kHz are indicated in parentheses.
In the main system clock 6.0 MHz operation, 0.5-second interval can be generated. Therefore, after switching to the subsystem clock, 0.5-second interval should be generated.
69
PD75237
(3)
Watch mode register (WM) The watch mode register (WM) is an 8-bit register to control the watch timer. Its format is shown in Fig. 4-30. The watch mode register is set by an 8-bit memory manipulation instruction. RESET input clears all bits to "0". Fig. 4-30 Watch Mode Register Format
7 WM7 6 0 5 WM5 4 WM4 3 0 2 WM2 1 WM1 0 WM0
Address F98H
Symbol WM
Count Clock (fW) Select Bit
0 WM0 1 Subsystem clock: fXT selected System clock divided output: fX selected 128
Operating Mode Select Bit
0 WM1 1 Fast watch mode Normal watch mode
(
fW 27
fW 214
: IRQW set at 0.5 sec
)
(
: IRQW set at 3.91 ms
)
Watch Operation Enable/Disable Bit
0 WM2 1 Watch operation enabled Watch operation stopped (frequency divider clear)
BUZ Output Frequency Select Bit
WM5 0 0 1 1 WM4 0 1 0 1 BUZ Output Frequency fW/24 (2.048 kHz) fW/23 (4.096 kHz) * Setting prohibited fW (32.768 kHz) *
*
Not supported with IE-75000-R
BUZ Output Enable/Disable Bit
0 WM7 1 BUZ output enabled BUZ output disabled
70
PD75237
4.7 (1)
TIMER/PULSE GENERATOR Timer/pulse generator functions The PD75237 incorporates one channel of timer/pulse generator which can be used as a timer or a pulse
generator. The timer/pulse generator has the following functions. (a) Functions available in the timer mode * 8-bit interval timer operation (IRQTPG generation) enabling the clock source to be varied at 5 levels * Square wave output to PPO pin Functions available in the PWM pulse generate mode * 14-bit accuracy PWM pulse output to the PPO pin (Used as a digital-to-analog converter and applicable to tuning) 15 * Interrupt generation of fixed time interval ( 2 = 5.46 ms : at 6.0 MHz operation) * fX
(b)
*
7.81 ms at 4.19 MHz operation If pulse output is not necessary, the PPO pin can be used as a 1-bit output port.
Note
If the STOP mode is set while the timer/pulse generator is in operation, miss-operation may result. To prevent that from occurring, preset the timer/pulse generator to the stop state using its mode register.
71
PD75237
(2)
Timer/pulse generator mode register (TPGM) The timer/pulse generator mode register (TPGM) is an 8-bit register to control timer/pulse generator operations. Its format is shown in Fig. 4-31. The TPGM is set by the 8-bit memory manipulation instruction. Bit 3 enables or disables the timer/pulse generator modulo register (MODH, MODL) contents to be transferred (reloaded) to the modulo latch and can be manipulated individually. The timer/pulse generator operation can be stopped and current consumption can be decreased by setting the TPGM1 to "0". RESET input clears all bits to "0". Fig. 4-31 Timer/Pulse Generator Mode Register Format
Address F90H 7 TPGM7 6 -- 5 TPGM5 4 3 2 0 1 0 Symbol TPGM
TPGM4 TPGM3
TPGM1 TPGM0
Timer/Pulse Generator Operating Mode Select Bit
0 TPGM0 1 Timer mode selected PWM pulse generate mode selected
Timer/Pulse Generator Operation Enable/Disable Bit
0 TPGM1 1 Timer/pulse generator operation enabled Timer/pulse generator operation stopped
Modulo Register Reload Enable/Disable Bit
0 TPGM3 1 Modulo register reload enabled Modulo register reload disabled
PPO Output Latch Data
0 TPGM4 1 Output 1 to PPO output latch Output 0 to PPO output latch
PPO Pin Output Select Bit Static/Pulse
0 TPGM5 1 Pulse (square wave/PWM) output from PPO pin Static output from PPO pin
PPO Pin Output Enable/Disable Bit
0 TPGM7 1 PPO pin output enabled PPO pin output disabled (high impedance)
72
PD75237
(3)
Configuration and operation for use in the timer mode The timer/pulse generator configuration for use in the timer mode is shown in Fig. 4-32. The timer mode is selected by setting TPGM bit 0 to "1". In the timer mode, enable modulo register reload
by setting TPGM3 to "1". In the timer mode, select the prescalar with modulo register L (MODL) and set the frequency or interrupt interval set value to modulo register H (MODH). Start the timer by resetting the TPGM1 from 0 to 1. The operation timing for MODH setting is shown in Fig. 4-33 and the frequency or interrupt interval setting is shown in Table 4-4. Square wave output or static output to the PPO pin can be switched. In the case of square wave output, set TPGM5 to "1" and TPGM7 to "1". Fig. 4-32 Block Diagram of Timer/Pulse Generator (Timer Mode)
Internal Bus
8 MODL
8 MODH
Modulo Register L (8)
TPGM3 (Set to "1")
Modulo Register H (8)
Modulo Latch H (8)
8
(
Match T F/F Selector
INTTPG IRQTPG Set Signal
)
Output Buffer
Comparator (8) Frequency Divider
fX 1/2 TPGM1
PPO CP 8
Set
Prescalar Select Latch (5) Clear
Count Register (8) Clear
TPGM4TPGM5 TPGM7
Note
If the timer is stopped in the timer operating mode, the IRQTPG may be set because the T F/F is set. Thus, when stopping the timer, do so with interruption disabled, and after the timer has stopped, clear the IRQTPG.
73
PD75237
Fig. 4-33 Timer Mode Operation Timing
CP MODH Count Register T F/F (PPO)
N
0
1
2
N-1
N
0
N
0
N
0
TPGM1 Set
IRQTPG Generated
Table 4-4 Modulo Register Setting (When fX = 6.0 MHz)
MODL Bits 2 to 6 6 0 5 0 4 0 3 0 2 1 Interrupt Generate Interval (fX = 6.0 MHz) 256( N+1) = 85.3 s to 10.9 ms fX 128( N+1) = 42.7 s to 5.45 ms fX 64( N+1) fX 32( N+1) fX 16( N+1) fX = 21.3 s to 2.73 ms = 10.7 s to 1.37 ms = 5.33 s to 683 s Square Wave Output Frequency (fX = 6.0 MHz) fX 256( N+1) = 91.6 Hz to 11.7 kHz
0
0
0
1
0
fX = 183 Hz to 23.4 kHz 128( N+1) fX 64( N+1) fX 32( N+1) fX 16( N+1) = 366 Hz to 46.9 kHz
0
0
1
0
0
0 1
1 0
0 0
0 0
0 0
= 732 Hz to 93.8 kHz = 1465 Hz to 188 kHz
(When fX = 4.19 MHz)
MODL Bits 2 to 6 6 0 5 0 4 0 3 0 2 1 Interrupt Generate Interval (fX = 4.19 MHz) 256( N+1) = 122 s to 15.6 ms fX 128( N+1) = 61.0 s to 7.81 ms fX 64( N+1) fX 32( N+1) fX 16( N+1) fX = 30.5 s to 3.91 ms = 15.3 s to 1.95 ms = 7.63 s to 977 s Square Wave Output Frequency (fX = 4.19 MHz) fX 256( N+1) = 64 Hz to 8 kHz
0
0
0
1
0
fX = 128 Hz to 16 kHz 128( N+1) fX 64( N+1) fX 32( N+1) fX 16( N+1) = 256 Hz to 32 kHz
0
0
1
0
0
0 1
1 0
0 0
0 0
0 0
= 512 Hz to 65 kHz = 1024 Hz to 131 kHz
Note
1. Only the above values can be set to MODL. Be sure to set "0" to bits 0, 1 and 7. 2. N is the MODH set value. "0" cannot be set to N. Be sure to set a value in the range from 1 to 255 to N.
74
PD75237
(4)
Configuration and operation for use in the PWM pulse generate mode The timer/pulse generator for use in the PWM pulse generate mode is shown in Fig. 4-34. The PWM pulse generate mode is selected by setting TPGM0 to "0". Pulse output is enabled by setting
TPGM5 and TPGM7 to "1". In the PWM mode, PWM pulse can be output from the PPO pin and the IRQTPG can be set at the fixed interval (215/fX = 5.46 ms : at 6.0 MHz operation)*1. The PWM pulse generated by the PD75237 is an active-low, 14-bit accuracy pulse. This pulse is converted to an analog voltage by integrating it using an external low-pass filter and can be applied for electronic tuning and DC motor control. (Refer to Fig. 4-35 Example of D/A Conversion Configuration with PD75237.) The PWM pulse is generated by combining the fundamental period determined by 210/fX (171 s: at 6.0 MHz operation)*2 and the sub period of 215/fX (5.46 ms: at 6.0 MHz operation)*1 and the time constant of the external low-pass filter can be shortened. The low-level width of the PWM pulse is determined by the 14-bit modulo latch value. The modulo latch value is determined as a result of transfer of MODH 8 bits to the most significant 8 bits of the modulo latch and MODL most significant 6 bits to the least significant 6 bits of the modulo latch. The digital-to analog converted output voltage is given as
VAN = Vref x
Modulo latch value 2 14
where Vref : External switching circuit reference voltage
In the PD75237, all 14 bits can be transferred simultaneously to the modulo latch after correct data has been written to MODH and MODL by the 8-bit manipulation instruction. This aims at preventing the PWM from being generated with an unstable value in the process of modulo latch rewrite. This transfer is called "reload" and is controlled by TPGM3. Note 1. Setting "0" to modulo register H (MODH) disables the PWM pulse generator to operate normally. Be sure to set to MODH a value in the range from 1 to 255. 2. When the least significant 2 bits of modulo register L (MODL) are read, an undefined value is read. 3. The fundamental period of the PWM pulse is 210/fX (171 s: at 6.0 MHz operation)*2. If the module latch is changed with a shorter period, the PWM pulse remains unchanged. * 1. 2. (5) 7.81 ms at 4.19 MHz operation 244 s at 4.19 MHz operation Static output to the PPO pin If pulse output is not necessary, the PPO pin can be used for normal static output. In this case, set output data to TPGM4 with TPGM5 and TPGM7 set to "0" and "1", respectively.
75
PD75237
Fig. 4-34 Timer/Pulse Generator Block Diagram (PWM Pulse Generate Mode)
Internal Bus
8 MODH
8 MODL
Modulo Register H (8)
TPGM3
Modulo Register L (6)
(2)
MODH (8)
MODL7-2 (6)
Modulo Latch (14) Output Buffer
TPGM1 fx 1/2
PWM Pulse Generator
Selector
PPO
Frequency Divider
INTTPG (IRQTPG Set Signal)
TPGM5
TPGM7
(
*
7.81 ms at 4.19 MHz operation
215 =5.46 ms : at 6.0 MHz operation) * fX
Fig. 4-35 Example of D/A Conversion Configuration with PD75237
PD75237
Vref
PWM PPO
Signal
Switching Circuit
Low-Pass Filter
VAN (Analog Voltage)
76
PD75237
4.8 (1)
EVENT COUNTER Event counter configuration The event counter of the PD75237 incorporates a noise eliminator and has a configuration shown in Fig.
4-36.
Fig. 4-36 Event Counter Block Diagram
Timer/Counter #0
GATEC.0
TM1.4
Selector
Noise Eliminator
fx
4
8-Bit Counter
TM1.2 T1
Overflow Flag
IRQT1
Internal Bus
Note
TI0/P13 pin is an external event pulse input pin which serves as timer/event counter #0 and event counter #1. Event counter functions The event counter has the following functions. (a) (b) (c) (d) Event counter operation Count state read function Count pulse edge specification Noise eliminating function
(2)
Selector
TI0/P13
77
PD75237
(3)
Event counter mode register The event counter mode register (TM1) is an 8-bit register to control the event counter. Its format is shown in Fig. 4-37. TM1 is set by an 8-bit memory manipulation instruction. Bit 3 is an event counter start bit and can be set independently. When the counter starts operating, bit 3 is automatically reset to "0". Fig. 4-37 Event Counter Mode Register Format
Address FA8H 7 0 6 0 5 0 4 TM14 3 TM13 2 TM12 1 0 0 0 Symbol TM1
Event Count Operation Enable/Disable Bit
0 TM12 1 Count operation enabled Count operation stopped (with count value held)
Event Counter Start Command Bit
Writing "1" clears the counter and IRQT1 flag. operation starts. If TM12 is "1", count
TM13
Count Pulse Edge Specification
0 TM14 1 TI0 input falling edge TI0 input rising edge
(4)
Overflow flag (IRQT1) The overflow flag is a flag which is set (1) by an overflow of the event counter count register and is cleared (0) by a count operation start command. Event counter control register (GATEC)
(5)
This is a register to select sampling with a sampling clock (fX/4). A pulse having a smaller width than that of two sampling clock cycles (8/fX) is eliminated as noise by a noise eliminator and a pulse having a width larger than that of the sampling clock is securely acknowledged as an interrupt signal. Its format is shown in Fig. 4-38. Fig. 4-38 Event Counter Control Register Format
Address FABH 3 0 2 0 1 0 0 GATEC0 Symbol GATEC
0 1
No sampling Sampling by fX/4
78
PD75237
4.9
SERIAL INTERFACE
The PD75237 incorporates two channels of clocked 8-bit serial interfaces. Table 4-5 gives differences between channel 0 and channel 1.
Table 4-5 Differences between Channels 0 and 1
Serial Transfer Mode and Function Clock selection Channel 0 fX/24 , fX/23 , TOUT F/F, external clock Channel 1 fX/24, fX/23, external clock MSB first Serial transfer end flag (EOT)
3-wire serial I/O Transfer mode MSB first/LSB first switchable Transfer end flag 2-wire serial I/O Serial bus interface Serial transfer end interrupt request flag (IRQCSI0) Use enabled
None
79
PD75237
(1)
Serial interface (channel 0) functions The following four modes are available for the PD75237 serial interface (channel 0). The functions of each mode are outlined below. * Operation stop mode This is the mode used when no serial transfer is performed. Low power consumption operation is possible in this mode. * 3-wire serial I/O mode 8-bit data is transferred using three lines of serial clock (SCK0), serial output (SO0) and serial input (SI0). The 3-wire serial I/O mode enables simultaneous transmission/reception, thus shortening the data transfer processing time. Since the start bit of 8-bit data for serial transfer can be switched between MSB and LSB, channel 0 can be connected to a device having either start bit. In the 3-wire serial I/O mode, channel 0 can be connected to the 75X series, 78K series and various types of peripheral I/O devices. * 2-wire serial I/O mode 8-bit data is transferred using two lines of serial clock (SCK0) and serial data bus (SB0 or SB1). Communication is possible with two or more devices by controlling the level of output to the two lines by software. Since the output level of SCK0 and SB0 (or SB1) can be controlled by software, any transfer format is applicable. Thus, the number of handshake lines previously required to connect two or more devices can be decreased and so the input/output ports can be used efficiently. * SBI mode (serial bus interface mode) This mode enables communication with two or more devices with two lines of serial clock (SCK0) and serial data bus (SB0 or SB1). This mode is compliant with the NEC serial bus format. In the SBI mode, the transmitter can output an "address" for selection of a serial communication target device on the serial data bus, a "command" to provide instructions to the target device and actual "data". The receiver can distinguish between "address", "command" and "data" by hardware. As in the 2wire serial I/O mode, this function enables the input/output ports to be used efficiently and the serial interface control portions of any applied program to be simplified.
(2)
Serial interface (channel 0) configuration Fig. 4-39 is a block diagram of serial interface (channel 0).
80
Fig. 4-39 Serial Interface (Channel 0) Block Diagram
Internal Bus
8/4 Bit Test CSIM0 8 8
8
Slave Address Register (SVA)
Bit Manipulation
Bit Test
(8)
Match Signal (8)
SBIC RELT CMDT
SO0 SET CLR Latch
Address Comparator
P03/SI0/SB1
Selector
Shift Register 0 (SIO0)
(8)
D
Q
P02/SO0/SB0
Selector
Busy /Acknowledge Output Circuit Bus Release /Command /Acknowledge Detector
RELD CMDD ACKD
ACKE BSYE
ACKT
P01/SCK0
Serial Clock Counter
INTCSI0
INTCSI0 INTCSI0 Control Circuit
(
Serial Clock Selector
IRQCSI0 Set Signal
3
)
P01 P01
Output Latch
Serial Clock Control Circuit
fx/2 4 fx/2 6 fx/2 TOUT F/F
(from Timer/Event Counter) External SCK0
PD75237
81
PD75237
(3)
Serial interface (channel 0) register functions (a) Serial operating mode register 0 (CSIM0) Fig. 4-40 shows a serial operating mode register 0 (CSIM0) format.
CSIM0 is an 8-bit register to specify the serial interface (channel 0) operating mode, serial clock and the wake-up function. An 8-bit memory manipulation instruction is used for CSIM0 operations. The higher 3 bits can be manipulated in 1-bit units. Use each bit name for bit manipulation. Read/write operation is enabled/disabled depending on the bit (refer to Fig. 4-40). Bit 6 is only enabled for test and the written data is invalidated. RESET input clears all bits to 0. Fig. 4-40 Serial Operating Mode Register 0 (CSIM0) Format (1/3)
Address FE0H 7 CSIE0 6 COI 5 WUP 4 3 2 1 0 Symbol CSIM0 Serial Clock Select Bit (W) Serial Interface Operating Mode Select Bit (W) Wake-Up Function Specify Bit (w) Signal (R) from Address Comparator Serial Interface Operation Enable/Disable Specify Bit (W)
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
Remarks
1. 2.
(R) : (W) :
Read only Write only
82
PD75237
Fig. 4-40 Serial Operating Mode Register 0 (CSIM0) Format (2/3) Serial Clock Select Bit (W)
Serial Clock CSIM01 0 0 1 1 CSIM00 3-Wire Serial I/O Mode 0 1 0 1
4
SBI Mode
2-Wire Serial I/O Mode
SCK0 Pin Mode Input
Input clock to SCK0 pin from outside. Timer/event counter output (T0) fX/2 (375 kHz, or 262 kHz) * fX/23(750 kHz, or 524 kHz) * fX/26(93.8 kHz, or 65.5 kHz) *
Output
*
Values in parentheses are when fX = 6.0 MHz or when fX = 4.19 MHz. Serial Interface Operating Mode Select Bit (W)
CSIM04 CSIM03 CSIM02 0 x 0 1 Operating Mode Bit Order of Shift Register 0 SIO07-0XA (transferred with MSB first) SIO00-7XA (transferred with LSB first) SB0/P02 N-ch open drain input/output SO0 Pin Function SI0 Pin Function
3-wire serial I/O mode
SO0/P02 (CMOS output)
SI0/P03 (input)
0 1 1 0 SBI mode SIO07-0XA (transferred with MSB first)
(
) ( ) (
P03 input
P02 input
SB1/P03 N-ch open drain input/output
)
0 1 1 1 2-wire serial I/O mode SIO07-0XA (transferred with MSB first)
(
SB0/P02 N-ch open drain input/output
P03 input
P02 input
SB1/P03 N-ch open drain input/output
)
Remarks
x : Don't care
Wake-Up Function Specify Bit (W)
0 WUP 1 IRQCSI0 is set upon termination of serial transfer in each mode. Used in SBI mode only. IRQCSI0 is set only when the address received after bus release matches the slave address register data (wake-up state). SB0/SB1 is high impedance.
Note
When WUP = 1 is set during BUSY signal output, BUSY is not released. In SBI, BUSY signal continues to be output up to the falling edge of the next serial clock (SCK0) after BUSY release. Ensure to set WUP = 1 after releasing BUSY and confirming that the SB0 (or SB1) pin has become high level.
83
PD75237
Fig. 4-40 Serial Operating Mode Register 0 (CSIMO) Format (3/3) Signal (R) from Address Comparator
Clear Condition (COI = 0) COI* When the slave address register (SVA) data unmatches the shift register 0 data. Set Condition (COI = 1) When the slave address register (SVA) data matches the shift register 0 data.
*
COI read is only valid before serial transfer and after its completion. Only undefined value is read during transfer. The COI data written by an 8-bit manipulation instruction is ignored.
Serial Interface Operation Enable/Disable Specify Bit (W)
Shift Register 0 Operation CSIE0 0 1 Shift operation disabled Shift operation enabled Serial Clock Counter Clear Count operation IRQCSI0 Flag Hold Settable SO0/SB0, SI0/SB1 Pins Dedicated to port 0 functions Functions in each mode and operations with port 0
Remarks
CSIE0 0 1 1 1
1.
Each mode can be selected by setting CSIE0, CSIM03 and CSIM02.
Operating Mode Operation stop mode 3-wire serial I/O mode SBI mode 2-wire serial I/O mode
CSIM03 CSIM02 x 0 1 1 x x 0 1
2.
CSIE0 0 1 0 0 0 1 1 1
P01/SCK0 pin becomes as follows depending on the settings of CSIE0, CSIM01 and CSIM00.
P01/SCK0 Pin Status Input port High impedance
CSIM01 CSIM00 0 0 0 1 1 0 1 1 0 0 1 0 1 1 0 1
High-level output
Serial clock output (high-level output)
84
PD75237
Remarks
3.
Clear CSIE0 during serial transfer using the following procedure. Disable interrupt by clearing the interrupt enable flag. Clear CSIE0. z Clear the interrupt request flag.
Example
1.
Select fx/24 for serial clock and generate serial interrupt IRQCSI0 upon termination of each serial transfer and select a serial transfer mode in the SBI mode using the SB0 pin as serial data bus. SEL MB15 ; Or CLR1 MBE MOV MOV XA, #10001010B CSIM0, XA ; CSIM0 10001010B
2.
Enable serial transfer in accordance with the CSIM0 contents. SEL MB15 ; Or CLR1 MBE SET1 CSIE0
85
PD75237
(b)
Serial bus interface control register (SBIC) Fig. 4-41 shows a serial bus interface control register (SBIC) format. SBIC is an 8-bit register which consists of a serial bus control bit and flags indicating various statuses
of input data received from the serial bus. SBIC is manipulated using a bit manipulation instruction. It cannot be manipulated using a 4-bit or 8-bit manipulation instruction. Read/write operation enable/disable depends on the bit (refer to Fig. 4-41). RESET input clears all bits to 0. Note Only the following bits can be used in the 3-wire and 2-wire serial I/O modes. * Bus release trigger bit (RELT) ........ SO0 latch set * Command trigger bit (CMDT) ........ SO0 latch clear Fig. 4-41 Serial Bus Interface Control Register (SBIC) Format (1/3)
Address FE2H
7 BSYE
6 ACKD
5 ACKE
4 ACKT
3 CMDD
2 RELD
1 CMDT
0 RELT
Symbol SBIC Bus Release Trigger Bit (W)
Command Trigger Bit (W) Bus Release Detect Flag (R) Command Detect Flag (R) Acknowledge Trigger Bit (W) Acknowledge Enable Bit (R/W) Acknowledge Detect Flag (R) Busy Enable Flag (R/W)
Remarks
1. 2. 3.
(R) Only read (W) Only write (R/W) Read/write enabled
86
PD75237
Fig. 4-41 Serial Bus Interface Control Register (SBIC) Format (2/3) Bus Release Trigger Bit (W)
RELT Bus release signal (REL) trigger output control bit. When set (RELT = 1), SO0 latch is set (1) and then the RELT bit is automatically cleared (0).
Note
Do not clear SB0 (or SB1) during serial transfer. Be sure to do so before transfer start or after transfer end.
Command Trigger Bit (W)
CMDT Command signal (CMD) trigger output control bit. When set (CMDT = 1), SO0 latch is cleared (0) and then the CMDT bit is automatically cleared (0).
Note
Do not clear SB0 (or SB1) during serial transfer. Be sure to do so before transfer start or after transfer end.
Bus Release Detect Flag (R)
Clearing Conditions (RELD = 0) RELD Transfer start instruction execution RESET input CSIE0 = 0 (refer to Fig. 4-40) 4 SVA and SIO0 mismatch upon address reception. Setting Conditions (RELD = 1)
Bus release signal (REL) detection
Command Detect Flag (R)
Clearing Conditions (CMDD = 0) CMDD Transfer start instruction execution Bus release signal (REL) detection RESET input 4 CSIE0 = 0 (refer to Fig. 4-40) Setting Conditions (CMDD = 1)
Command signal (CMD) detection
Acknowledge Trigger Bit (W)
ACKT Setting this bit after termination of transfer outputs ACK in synchronization with the next SCK0. After output of ACK signal, this bit is automatically cleared (0).
Note
1. Do not set (1) this bit during serial transfer. 2. ACKT cannot be cleared by software. 3. When setting ACKT, set ACKE = 0.
Acknowledge Enable Bit (R/W)
0 ACKE 1 When set after termination of transfer Automatic output of acknowledge signal (ACK) is disabled (output by ACKT enabled). When set before termination of transfer ACK is output in synchronization with the 9th clock of SCK0. ACK is output in synchronization with SCK0 just after execution of a set instruction.
87
PD75237
Fig. 4-41 Serial Bus Interface Control Register (SBIC) Format (3/3) Acknowledge Detect Flag (R)
Clearing Conditions (ACKD = 0) ACKD Transfer start instruction execution RESET input Setting Conditions (ACKD = 1) Acknowledge signal (ACK) detection (at the rising edge of SCK0)
Busy Enable Bit (R/W)
0 1 Busy signal automatic output disabled Busy signal output stopped at the falling edge of SCK0 just after clear instruction execution. Busy signal output at the falling edge of SCK0 following the acknowledge signal.
BSYE
Example
1.
Output the command signal. SEL MB15 ; Or CLR1 MBE SET1 CMDT Identify the receive data type by testing RELD and CMDD for proper processing. Set WUP = 1 for this interruput routine so that processing is carried out only in the case of a match address. SEL SKF BR SKT MB15 RELD !ADRS CMDD ; RELD test ; CMDD test
2.
BR !DATA CMD : ....................................... ; Command interpret DATE : ....................................... ; Data processing ADRS : ....................................... ; Address decode
88
PD75237
(c)
Shift register 0 (SIO0) Fig. 4-42 shows a shift register 0 peripheral configuration. SIO0 is an 8-bit register which executes parallel-to-serial conversion and carries out serial transmission/reception (shift operation) in synchronization with a serial clock. Serial transfer is started by writing data to SIO0. In transmission, the data written to SIO0 is output to the serial output (SO0) or serial data bus (SB0/SB1). In reception, data is read from the serial input (SI0) or SB0/SB1 to SIO0. This register can be read/written by an 8-bit manipulation instruction. RESET input during operation makes the SIO0 value undefined. RESET input in the standby mode holds the SIO0 value. Shift operation stops after 8-bit transmission /reception. Fig. 4-42 Shift Register 0 peripheral Configuration
Internal Bus
Address Comparator
RELT CMDT
Shift Register 0
SO0 Latch SET D CLK CLR Q
CSIM0 Shift Clock
BUSY/ACK N-ch Open Drain Output
SIO0 read and serial transfer start (write) are enabled at the following timings. * Serial interface operation enable/disable bit (CSIE0) = 1 except when CSIE0 is set to "1" after data write to the shift register. * When the serial clock is masked after 8-bit serial transfer. * When SCK0 is at a high level Be sure to write/read data to SIO0 when SCK0 is at a high level. In the 2-wire serial I/O or SBI mode, the data bus has a configuration that the input pins serve as output pins and vice versa. Each output pin has an N-ch open drain configuration. Thus, set FFH to SIO0 for the device for data reception.
89
PD75237
(d)
Slave address register (SVA) The slave address register (SVA) has the following two functions. Only write is enabled for the SVA by an 8-bit manipulation instruction.
RESET input makes the SVA value undefined. RESET input in the standby mode holds the SVA value. * Slave address detection [SBI mode] Use this mode to connect the PD75237 as a slave device to the serial bus. The SVA is an 8-bit register for the slave to set the slave address value (own specification number). The master outputs a slave address for particular slave selection to the connected slave. These two date (salve address and SVA values output from the master) are compared by an address comparator. When they match, the slave has been selected. In this case, bit 6 (COI) of the serial operating mode register 0 (CSIM0) is set to "1". Note 1. The slave selection or non-selection status is checked by detecting the matching of the slave address received after bus release (RELD = 1). Use the address match interrupt (IRQCSI0) to be normally generated with WUP = 1 to detect the matching. Thus, detect selection or non-selection by slave address when WUP = 1. 2. If selection or non-selection is to be detected without using an interrupt when WUP = 0, do so by transmitting/receiving the command preset by a program without using the method of detecting address matching.
* Error detection [2-wire serial I/O and SBI modes] When an address, a command and data are to be transmitted using the PD75237 as the master device or data is to be transmitted using the PD75237 as the slave device, the SVA detects errors. (4) Various types of signals Table 4-6 gives a list of various types of signals. Figs. 4-43 to 4-48 show the various types of signals and flag operation.
90
Table 4-6 Various Types of Signals in SBI Mode (1/2)
Signal Name
Output Device
Definition Rising edge of SB0/SB1 when
Timing Chart
Output Condition * RELT set
Effect on Flag * RELD set
Meaning of Signal CMD signal is output to
Bus release signal (REL) Master
SCK0 = 1
SCK0 SB0/SB1 "H"
* CMDD clear indicate that transmit data is an address.
Falling edge of SB0/SB1 when SCK0 = 1 Command signal (CMD) Master
* CMDT set
* CMDD set
i) Transmit data is an address after REL signal
SCK0 SB0/SB1
"H"
output ii) No REL signal output. Transmit data is a command.
Low-level signal to be output Acknowledge signal (ACK) Master/ slave to SB0/SB1 during one-clock period of SCK0 after completion of serial reception [Synchronous busy signal] Busy signal (BUSY) Slave Low-level signal to be output to SB0/SB1 following the acknowledge signal High- level signal to be output to before serial transfer start or after its compleltion Ready signal Slave (READY)
SB0/SB1 D0 SB0/SB1 D0 ACK BUSY READY SCK0 9 ACK BUSY READY
ACKE = 1 ACKT set
* ACKD set
Completion of reception
[Synchronous Busy Output] * BSYE = 1 -- Serial reception disabled because of processing
BSYE = 0 Execution of an instruction for data write to SIO0 (transfer start command)
--
Serial reception enabed
PD75237
91
92
Signal Name Output Device Definition Serial clock (SCK0) Master Address (A7 to 0) Master Command (C7 to 0) Master Data (D7 to 0) Master/ slave
Table 4-6 Various Types of Signals in SBI Mode (2/2)
Timing Chart
Output Condition Execution of an instruction for data write to SIO0 when CSIE0 = 1 (serial transfer start command)*2
Effect on Flag
Meaning of Signal
Synchronous clock to ouput address, command, data, ACK signal and synchronous BUSY signal. Address, command and data are transferred by the first eight clocks. 8-bit data to be transferred in synchronization with SCK0 after output of REL and CMD signals
SCK0
1
2
7
8
9
10
SB0/SB1
IRQCSI0 set Timing of signal output (rising edge to the serial data bus of 9th clock) *1
SCK0
1
2
7
8
Address value of slave device on the serial bus
SB0/SB1 REL CMD
8-bit data to be transferred in synchronization with SCK0 after output of CMD signal only without REL signal output
SCK0
1
2
7
8
Command and message for the slave device
SB0/SB1 CMD
8-bit data to be transferred in synchronization with SCK0 without output of REL and CMD signals
SCK0
1
2
7
8
Numeric value to be processed by a slave or master device
SB0/SB1
* 1.
When WUP = 0, IRQCSI0 is always set at the rising edge of the 9th clock of SCK0. When WUP = 1, an address is received. Only when the received address matches the slave adress register (SVA) value, IRQCSI0 is set at the rising edge of the 9th clock of SCK0. Transfer starts after the BUSY state is changed to the READY state.
PD75237
2.
PD75237
Fig. 4-43 RELT, CMDT, RELD and CMDD (Master) Operations
Transfer Start Directive SIO0
SCK0
"H"
SO0 Latch RELT CMDT
RELD
CMDD
Fig. 4-44 RELT, CMDT, RELD and CMDD (Slave) Operations
Transfer Start Directive Write to SIO0
SIO0
SCK0
1
2
7
8
SO0 Latch RELT (Master) CMDT (Master)
D7
D6
D1
D0
When the address matches
RELD
When the address does not match
CMDD
FIg. 4-45 ACKT Operations
Set after completion of transfer
SCK0
6
7
8
9
ACK signal is output during 1-clock period just after setting
SB0/SB1
D2
D1
D0
ACK
ACKT
When set during this period
Note
Do not set ACKT just before termination of transfer.
93
PD75237
Fig. 4-46 ACKE Operation (a) When ACKE = 1 upon completion of transfer
SCK0
1
2
7
8
9
SB0/SB1 ACKE
D7
D6
D2
D1
D0
ACK
ACK signal is output at the 9th clock
When ACKE=1 at this point
(b)
When set after completion of transfer
SCK0 6 7 8 9
SB0/SB1 ACKE
D2
D1
D0
ACK
ACK signal is output during 1-clock period just after setting
When set during this period and ACKE=1 at the falling edge of the next SCK0.
(c)
When ACKE = 0 upon completion of transfer
SCK0 1 2 7 8 9
ACK signal is not output
SB0/SB1 ACKE
D7
D6
D2
D1
D0
When ACKE = 0 at this point
(d)
When the ACKE = 1 period is short
SCK0
SB0/SB1 ACKE
ACK signal is not output
When set and cleared during this period and ACKE=0 at the falling edge of ACK0
94
PD75237
Fig. 4-47 ACKD Operations (a) When ACK signal is output during the 9th clock period of SCK0.
Transfer Start Directive
SIO0
Transfer Start
SCK0 6 7 8 9
SB0/SB1
D2
D1
D0
ACK
ACKD
(b)
When ACK signal is output after the 9th clock of SCK0
SIO0
Transfer Start Directive
Transfer Start
SCK0 6 7 8 9
SB0/SB1
D2
D1
D0
ACK
ACKD
(c)
Clear timing with transfer start command during BUSY
Transfer Start Directive SIO0
SCK0
6
7
8
9 ACK BUSY
SB0/SB1
D2
D1
D0
D7
D6
ACKD
Fig. 4-48 BSYE Operation
SCK0
6
7
8
9
SB0/SB1
ACK
BUSY
BSYE
When BSYE=1 at this point
When reset during this period and BSYE=0 at the falling edge of SCK0
95
PD75237
(5)
Serial interface (channel 0) operations (a) Operation stop mode
The operation stop mode is used when serial transfer is not carried out. Power consumption is decreased in this mode. In this mode, shift register 0 does not carry out shift operation and thus can be used as a normal 8bit register. RESET input sets the operation stop mode. The P02/SO0/SB0 pin and P03/SI0/SB1 pins are fixed to the input port. P01/SCK0 can be used as an input port by setting serial operating mode register 0. (b) 3-wire serial I/O mode operations The 3-wire serial I/O mode allows connection with the methods employed with another 75X series and
78K series. Communication is carried out using three lines of serial clock (SCK0), serial output (SO0) and serial input (SI0). (i) Communication The 3-wire serial I/O mode is used for data transmission and reception in 8-bit units. Bit-wise data transmission/reception is carried out in synchronization with the serial clock. Shift operation of shift register 0 is carried out at the falling edge of serial clock (SCK0). Transmit data is held at the SO0 latch and output from the SO0 pin. Receive data input to the SI0 pin is latched to the shift register 0 at the rising edge of SCK0. Shift register 0 operation automatically stops upon termination of 8-bit transfer and the interrupt request flag (IRQCSI0) is set. Fig. 4-49 3-Wire Serial I/O Mode Timing
SCK0
1
2
3
4
5
6
7
8
SI0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
IRQCSI0
Transfer start at the falling edge of SCK0 Execution of data write instruction to SIO0 (Transfer Start Directive)
End of Transfer
96
PD75237
The SO0 pin serves as CMOS output to output the SO0 latch status. Thus, the SO0 pin output status can be manipulated by setting the RELT and CMDT bits. However, do not carry out this manipulation during serial transfer. The SCK0 pin can control the output status by manipulating the P01 output latch in the output mode (internal system clock mode) (refer to 4.9 (7) SCK0 pin output manipulation). (ii) MSB/LSB first switching The 3-wire serial I/O mode has a function which allows MSB-first or LSB-first transfer to be selected.
Fig. 4-50 shows shift register 0 (SIO0) and internal bus configurations. As shown in Fig. 4-50, MSB/ LSB can be reversed and read/written. MSB/LSB first switching can be specified by bit 2 of serial operating mode register 0 (CSIM0).
Fig. 4-50 Transfer Bit Switching Circuit
7 6
Internal Bus
1 0
LSB First MSB First Read/Write Gate Read/Write Gate
SI0
Shift Register 0 (SIO0)
D
Q
SO0 Latch
SO0 SCK0
First bit switching is realized by switching the bit order of data write to the shift register 0 (SIO0). The SIO0 shift order remains the same. Thus, switch the MSB/LSB first bit before writing data to the shift register 0.
97
PD75237
(c)
2-wire serial I/O mode operations The 2-wire serial I/O mode can be applied to any communication format by program. Communication is basically carried out using two lines of serial clock (SCK0) and serial data input/
output (SB0 or SB1). (i) Communication The 2-wire serial I/O mode is used for data transmission and reception in 8-bit units. Bit-wise data transmission/reception is carried out in synchronization with the serial clock. Shift operation of shift register 0 is carried out at the falling edge of serial clock (SCK0). Transmit data is held at the SO0 latch and output from the SB0/P02 (or SB1/P03) pin with MSB set as the first bit. Receive data input from the SB0 (or SB1) pin at the SCK0 rising edge is latched to the shift register 0. Upon termination of 8-bit transfer, the shift register 0 operation automatically stops and the interrupt request flag (IRQCSI0) is set. Fig. 4-51 2-Wire Serial I/O Mode Timing
SCK0
1
2
3
4
5
6
7
8
SB0/SB1
D7
D6
D5
D4
D3
D2
D1
D0
IRQCSI0
End of Transfer Transfer start at the falling edge of SCK0 Execution of data write instruction to SIO0 (Transfer Start Directive)
Since the pin specified for the serial data bus of the SB0 (or SB1) pin becomes an N-ch open drain input/ output, it must be pulled up externally. Since the SB0 (or SB1) pin outputs the SO0 latch status, the SB0 (or SB1) pin status can be manipulated by setting the RELT and CMDT bits. However, do not carry out this operation during serial transfer. The SCK0 pin can control the output status by manipulating the P01 output latch in the output mode (internal system clock mode) (refer to 4.9 (7) SCK0 pin output manipulation).
98
PD75237
(d)
SBI mode operations SBI (serial bus interface) is a high-speed serial interface method compliant with the NEC serial bus format. SBI is a single master high-speed serial bus based on the format with bus configuration functions added to the clocked serial synchronization I/O method so that communication can be carried out with two or more devices using two signal conductors. Thus, the number of ports used and that of wires on the board can be decreased for serial bus configuration with two or more microcomputers and peripheral ICs. Fig. 4-52 shows the SBI system configuration example. Fig. 4-52 SBI System Configuration Example
Master CPU PD75237
Slave CPU PD75237
SB0 (AB1)
SB0 (SB1)
Address 1
SCK0
SCK0
Slave CPU
SB0 (SB1)
Address 2
SCK0
Slave IC
SB0 (SB1)
Address N
SCK0
Note 1. 2.
Because in the SBI the serial data bus pin SB0 (or SB1) is an open drain output, the serial data bus line is wired-OR. A pull-up resistor is necessary for the serial data bus line. For master/slave replacement, a pull-up resistor is necessary for SCK0 because serial clock line (SCK0) input/output switching is executed asynchronously between the master and slave.
99
PD75237
(i)
SBI functions * Address/command/data identification SBI distinguishes serial data between address, command and data. * Chip select function by address The master executes slave chip selection by address transmission. * Wake-up function The slave can easily make an address receive judgment (chip select judgment) using the wake- up function (which can be set/cancelled by software). When the wake-up function is set, an interrupt (IRQCSI0) is generated upon reception of a match address. Thus, when communication is carried out with two or more devices, CPUs except the selected slave can operate irrespective of serial communication. * Acknowledge signal (ACK) control function Acknowledge signal is controlled to confirm serial data reception. * Busy signal (BUSY) control function The busy signal is controlled to inform the slave busy status. Fig. 4-53 SBI Transfer Timing
Address Transfer
SCK0 8 9
SB0/SB1
A7
A0
ACK
BUSY
Bus Release Signal Command Transfer Command Signal
SCK0
9
SB0/SB1
C7
C0
ACK
BUSY
READY
Data Transfer
SCK0
8
9
SB0/SB1
D7
D0
ACK
BUSY
READY
100
PD75237
(ii)
Communication In the SBI, the master normally selects one slave device for communication target from among two or more devices by outputting an "address" to the serial bus. After the communication target device has been determined, serial communication is achieved through command and data transmission/reception between the master and slave devices. Figs. 4-54 to 4-57 show the timing charts of data communication. In the SBI mode, shift operation of shift register 0 is carried out at the falling edge of serial clock (SCK0) and transmit data is output from the SB0/P02 or SB1/P03 pin with MSB as the first bit. Receive data input to the SB0 (or SB1) pin at the rising edge of SCK0 is latched to the shift register 0.
101
102 Fig. 4-54 Address Transmission from Master Device to Slave Device (WUP = 1)
Master Device Processing (Transmitter Side) Program Processing
CMDT RELT CMDT Set Set Set Write to SIO0
Interrupt Servicing (Preparation for the Next Serial Transfer) IRQCSI0 Generation
Hardware Operation
Serial Transmission
ACKD Set
SCK0 Stop
Transfer Line SCK0 Pin 1 2 3 4 5 6 7 8 9
SB0 Pin A7 A6 A5 A4 A3 A2 A1 A0 ACK BUSY READY
Address Slave Device Processing (Receiver Side) Program Processing
WUP 0
ACKT Set BUSY Clear
Hardware Operation
CMDD CMDD CMDD
Set Clear RELD Set Set
Serial Reception
IRQCSI0 Generation
ACK Output
BUSY Output
BUSY Clear
(When SVA = SIO0)
PD75237
Fig. 4-55 Command Transmission from Master Device to Slave Device
Master Device Processing (Transmitter Side) Program Processing
CMDT Set Write to SIO0
Interrupt Servicing (Preparation for the Next Serial Transfer) IRQCSI0 Generation
Hardware Operation
Serial Transmission
ACKD Set
SCK0 Stop
Transfer Line SCK0 Pin 1 2 3 4 5 6 7 8 9
SB0 Pin
C7
C6
C5
C4
C3
C2
C1
C0
ACK
BUSY
READY
Command Slave Device Processing (Receiver Side) Program Processing
SIO0 Read Command Analysis ACKT Set BUSY Clear
Hardware Operation
CMDD Set
Serial Reception
IRQCSI0 Generation
ACK Output
BUSY Output
BUSY Clear
PD75237
103
104 Fig. 4-56 Data Transmission from Master Device to Slave Device
Master Device Processing (Transmitter Side) Program Processing
Write to SIO0
Interrupt Servicing (Preparation for the Next Serial Transfer) IRQCSI0 Generation
Hardware Operation
Serial Transmission
ACKD Set
SCK0 Set
Transfer Line SCK0 Pin 1 2 3 4 5 6 7 8 9
SB0 Pin
D7
D6
D5
D4
D3
D2
D1
D0
ACK
BUSY
READY
Data Slave Device Processing (Receiver Side) Program Processing
SIO0 Read ACKT Set BUSY Clear
Hardware Operation
Serial Reception
IRQCSI0 Generation
ACK Output
BUSY Output
BUSY Clear
PD75237
Fig. 4-57 Data Transmission from Slave Device to Master Device5
Master Device Processing (Receiver Side)
FFH Write to SIO0 SIO0 Read ACKT Set FFH Write to SIO0
Program Processing
Receive Data Processing
Hardware Operation
SCK0 Stop
Serial Reception
IRQCSI0 Generation
ACK Output
Serial Reception
Transfer Line SCK0 Pin 1 2 3 4 5 6 7 8 9 1 2
SB0 Pin
BUSY
READY
D7
D6
D5
D4 Data
D3
D2
D1
D0
ACK
BUSY
READY
D7D6
Slave Device Processing (Transmitter Side) Program Processing
Write to SIO0 Write to SIO0
Hardware Operation
BUSY Clear
Serial Transmission
IRQCSI0 Generation
ACKD BUSY Output Output
BUSY Clear
PD75237
105
PD75237
(6)
Transfer start in each mode In each of the 3-wire and 2-wire serial I/O modes and the SBI mode, serial transfer is started by setting transfer data to the shift register 0 (SIO0) under the following two conditions. * Serial interface operation enable/disable bit (CSIE0) = 1 * The internal serial clock has stopped or SCK0 is at high level after 8-bit serial transfer.
Note
Transfer does not start if CSIE0 is set to "1" after data is written to the shift register 0. Serial transfer automatically stops and the interrupt request flag (IRQCSI0) is set upon termination of 8-bit transfer.
[2-wire serial I/O mode transfer start precautions] Note Because it is necessary to turn off the N-ch transistor upon data reception, write FFH to SIO0 in advance. [SBI mode transfer start precautions] Note 1. Because it is necessary to turn off the N-ch transistor upon data reception, write FFH to SIO0 in advance. However, in the case of wake-up function specify bit (WUP) = 1, the N-ch transistor remains OFF. Thus, it is not necessary to write FFH to SIO0 before reception. 2. If data is written to SIO0 when the slave is busy, the written data is not lost. Transfer starts when the busy status is cancelled and the SB0 (or SB1) input becomes high level (ready status). Example The RAM data specified by the HL register is transferred to SIO0 and simultaneously the SIO0 data is fetched into the accumulator and serial transfer is started. MOV SEL XCH XA, @HL MB15 XA, SIO0 ; Transmit data is fetched from the RAM. ; Or CLR1 MBE ; Transmit data is exchanged with receive data and transfer is started.
106
PD75237
(7)
SCK0 pin output manipulation Because the SCK0/P01 pin incorporates an output latch, static output is possible by software in addition to normal serial clocks. P01 output latch manipulation enables to set any number of SCK0 by software (SO0/SB0/SB1 pin is controlled by the RELT and CMDT bits of SBIC). SCK0/P01 pin output manipulation is described below. Set the serial operating mode register 0 (CSIM0) (SCK0 pin: output mode, serial operation: enabled). While serial transfer is stopped, SCK0 from the serial clock control circuit remains 1. Manipulate the P01 output latch by a bit manipulation instruction.
Example
1 clock SEL MOV MOV CLR1 SET1
output to SCK0/P01 pin by software. MB15 ; Or CLR1 MBE XA,#10000011B ; SCK0(fX/23), output mode CSIM0,XA 0FF0H.1 0FF0H.1 ; SCK0/P010 ; SCK0/P011
Fig. 4-58 SCK0/P01 Pin Configuration
Address FF0H.1 P01/SCK0 To Internal Circuit P01 Output Latch From Serial Clock Control Circuit
SCK0 CSIE0 = 1 and CSIM01 and CSIM00 00
The P01 output latch is mapped at bit 1 of address FF0H. RESET signal generation sets the P01 output latch to "1". Note 1. It is necessary to set the P01 output latch to 1 during normal serial transfer. 2. The P01 output latch address cannot be set by "PORT0.1" as shown below. Describe address (0FF0H.1) directly for the operand. However, it is necessary to preset MBE = 0 or (MBE = 1 and MBS = 15) for instruction execution. CLR1 PORT0.1 Use disabled SET1 PORT0.1 CLR1 0FF0H.1 Use enabled SET1 0FF0H.1
107
PD75237
(8)
Serial interface (channel 1) functions The following two modes are available to the PD75237 serial interface (channel 1). The summary of each mode is shown below. * Operation stop mode The operation stop mode is used when serial transfer is not carried out. Power consumption is decreased in this mode. * 3-wire serial I/O mode 8-bit data transfer is carried out using three lines of serial clock (SCK1), serial output (SO1) and serial input (SI1). In the 3-wire serial I/O mode which enables simultaneous transmission and reception, the data transfer rate is improved. The first bit of 8-bit data for serial transfer is fixed to MSB. In the 3-wire serial I/O mode, channel 1 can be connected to the 75X series, 78K series and various types of peripheral I/O devices.
5
(9)
Serial interface (channel 1) configuration Fig. 4-59 shows a serial interface (channel 1) block diagram.
108
Fig. 4-59 Serial Interface (Channel 1) Block Diagram
Internal Bus Bit Manipulation bit7 SIO1 Shift Register 1 (8) Serial Operating Mode Register (8) Bit Manipulation 0 CSIM1
8 bit0 P83/SI1
SIO1 Write Signal (Serial Start Signal) 7
8
P82/SO1
Clear Overflow Serial Clock Counter (3) Set Serial Transfer End Flag (EOT)
P81/SCK1
Clear R Q S Serial Clock Selector fx/23
fx/24
PD75237
109
PD75237
(10) Serial interface (channel 1) register functions (a) Serial operating mode register 1 (CSIM1)
Fig. 4-60 shows a serial operating mode register 1 (CSIM1) format. CSIM1 is an 8-bit register to specify the serial interface (channel 1) operating mode and serial clock. It is manipulated by an 8-bit memory manipulation instruction. The higher 1 bit can be manipulated bit-wise. Use each bit name for bit manipulation. RESET input clears all bits to 0. Fig. 4-60 Serial Operating Mode Register 1 Format
Address FC8H 7 CSIE1 6 0 5 0 4 0 3 0 2 0 1 0 Symbol CSIM1
CSIM11 CSIM10
Serial Clock Select Bit (W)
CSIM11 0 0 1 1 CSIM10 0 1 0 1 Serial Clock 3-Wire Serial I/O Mode External input clock to SCK1 pin Setting disabled fx/2 (375 kHz, or 262 kHz) * fx/23 (750 kHz, or 524 kHz) *
4
SCK Pin Mode Input -- Output
*
Values in parentheses are when fX = 6.0 MHz or fX = 4.19 MHz.
Serial Interface Operation Enable/Disable Specify Bit (W)
Shift Register 1 Operation Serial Clock Counter IRQCSI Flag Clear Count operation Hold Settable SO1 and SI1 Pins Dedicated to port 8 functions Functions in each mode and operations with port 8
5 5
CSIE1
0 1
Shift operation disabled Shift operation enabled
Note
Be sure to write "0" to bits 2 to 6 of the serial operating mode register.
110
PD75237
(b)
Shift register 1 (SIO1) SIO1 is an 8-bit register which executes parallel to serial conversion and carries out serial transmission/ reception (shift operation) in synchronization with a serial clock. Serial transfer is started by writing data to SIO1. In transmission, the data written to SIO1 is output to the serial output (SO1). In reception, data is read from the serial input (SI1) to SIO1. This register can be read/written by an 8-bit manipulation instruction. RESET input during operation makes the SIO1 value undefined. RESET input in the standby mode holds the SIO1 value. Shift operation stops after 8-bit transmission/reception. SIO1 read and serial transfer start (write) are enabled at the following timings. * Serial interface operation enable/disable bit (CSIE1) = 1 except when CSIE1 is set to "1" after data write to the shift register. * When the serial clock is masked after 8-bit serial transfer. * When SCK1 is at a high level.
111
PD75237
(11) Serial interface (channel 1) operations (a) Operation stop mode
The operation stop mode is used when serial transfer is not carried out. Power consumption is decreased in this mode. In this mode, shift register 1 does not carry out shift operation and thus can be used as a normal 8bit register. RESET input sets the operation stop mode. The P82/SO1 pin and P83/SI1 pin are fixed to the input port. P81/SCK1 can be used as an input port by setting serial operating mode register 1. (b) 3-wire serial I/O mode operations
The 3-wire serial I/O mode allows connection with the methods employed with another 75X series and 78K series, etc. Communication is carried out using three lines of serial clock (SCK1), serial output (SO1) and serial input (SI1). The 3-wire serial I/O mode is used for data transmission and reception in 8-bit units. Bit-wise data transmission/reception is carried out in synchronization with the serial clock. Shift operation of shift register 1 is carried out at the falling edge of serial clock (SCK1). Transmit data is held at the SO1 latch and output from the SO1 pin. Receive data input to the SI1 pin is latched to the shift register 1 at the rising edge of SCK1. Shift register 1 operation automatically stops upon termination of 8-bit transfer and the serial transfer end flag (EOT) is set. Fig. 4-61 3-Wire Serial I/O Mode Timing
SCK1
1
2
3
4
5
6
7
8
SI1
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO1
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
EOT Transfer start at the falling edge of SCK1 Execution of data write instruction to SIO1 (Transfer Start Directive) End of Transfer
112
PD75237
4.10 A/D CONVERTER The PD75237 incorporates an 8-bit resolution A/D converter with 8-channel analog inputs (AN0 to AN7). The A/D converter employs successive approximation. (1) A/D converter configuration Fig. 4-62 shows an A/D converter configuration. Fig. 4-62 A/D Converter Block Diagram
Internal Bus
8
0
ADM6 ADM5 ADM4 SOC
EOC
0
0
8
AN0 AN1 AN2 AN3 Multiplexer AN4 AN5 AN6 AN7 Simple & Hold Circuit
Control Circuit
+ - Comparator
SA Register (8)
8
Tap Decoder
AV REF R/2 R R R R/2
AV ss
113
PD75237
(2)
A/D converter pin functions (a) AN0 to AN7
These are 8-channel analog signal input pins to the A/D converter. An analog signal to undergo A/ D conversion is input to these pins. The A/D converter incorporates a sample hold circuit. The analog input voltage is internally held during A/D conversion. (b) AVREF and AVSS The A/D converter reference voltage is input to these pins. Signals input to AN0 to AN7 are converted to digital signals in accordance with the voltage applied
5
between AVREF and AVSS. AVSS should always be set to the same voltage as VSS. (c) AVDD
AVDD is a power supply pin for the A/D converter. It should be set to the same voltage as VDD, even when the A/D converter is not used, or in standby mode. (3) A/D conversion mode register
The A/D conversion mode register (ADM) is an 8-bit register for analog input channel selection, conversion start command and conversion end detection (see Fig. 4-63). The ADM is set by an 8-bit manipulation instruction. The bit 2 conversion end detection flag (EOC) and the bit 3 conversion start command bit (SOC) can be manipulated in bit units. RESET input initializes the ADM to 04H (only EOC is set to "1" and all other bits are cleared to "0").
114
PD75237
Fig. 4-63 A/D Conversion Mode Register Format
Address FD8H 7 0 6 ADM6 5 ADM5 4 ADM4 3 SOC 2 EOC 1 0 0 0 Symbol ADM
Conversion End Detection Flag
0 EOC 1 Being converted End of conversion
Conversion Start Directive Bit
Setting this bit starts A/D conversion. SOC Upon conversion start, this bit is automatically cleared.
Analog Channel Select Bit
ADM6 0 0 0 0 1 1 1 1 ADM5 0 0 1 1 0 0 1 1 ADM4 0 1 0 1 0 1 0 1 Analog Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Note
A/D conversion starts with a maximum delay of 24/fX sec (2.67 s: at 6.0 MHz operation)* after SOC setting (refer to 4.10 (5) A/D converter operations).
*
3.81 s at 4.19 MHz operation
115
PD75237
(4)
SA register (SA) The SA register (Successive Approximation Register) is an 8-bit register to store the result of A/D conversion by successive approximation. The SA register is read by an 8-bit manipulation instruction. Data cannot be written to this register by software. RESET input sets the SA register undefined.
(5)
A/D converter operations The analog input signal to undergo A/D conversion is specified by setting bits 6, 5 and 4 (ADM6, 5 and 4) of the A/D conversion mode register. A/D conversion is started by setting (1) ADM bit 3 (SOC). SOC is automatically cleared (0) after the setting. A/D conversion is executed using successive approximation by hardware and the 8-bit conversion result data is stored into the SA register. Upon termination of conversion, bit 2 (EOC) of ADM is set (1). Fig. 4-64 is an A/D conversion timing chart. Use the A/D converter as follows.
4
Select the analog input channel (ADM 6, 5 and 4 setting). Instruct A/D conversion start (SOC setting). Wait for A/D conversion to terminate (wait for EOC to be set or wait with a software timer). Read the A/D conversion result (SA register reading).
Note
1. and can be carried out simultaneously. 2. A maximum delay of 24/fX sec (2.67 s: at 6.0 MHz operation)* occurs from A/D conversion start to EOC clear after SOC setting. Thus, test EOC after the passage of time indicated in Table 4-7 after SOC setting. Table 4-7 shows A/D conversion times as well.
*
3.81 s at 4.19 MHz operation Table 4-7 SCC and PCC Settings
SCC and PCC Set Value SCC3 SCC0 PCC1 0 0 0 0 1 1 0 1 1 x x x 0 1 x x Conversion operation stopped PCC0 0 1 A/D Conversion Time Wait time till the end of A/D conversion after SOC setting 3 machine cycles 11 machine cycles 21 machine cycles 42 machine cycles Wait not required --
Wait time till EOC test after SOC setting Wait not required
1 machine cycle 168/fx (28 s : at 6.0 2 machine cycles MHz operation)* 4 machine cycles Wait not required --
* 40.1 s at 4.19 MHz operation Remarks x : Don't care
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PD75237
Fig. 4-64 A/D Conversion Timing Chart
SOC
EOC
SA Register
Previous Data
Undefined
Conversion Result
Time until A/D Conversion Start (2 4/fX x sec max.)
Sampling A/D Conversion
168/fX sec (28 s: at 6.0 MHz operation)*
*
40.1 s at 4.19 MHz operation
(6)
Standby mode precautions The A/D converter operates with the main system clock. Thus, the converter operation stops in the STOP
mode or in the HALT mode with the subsystem clock. In this case also, current flows to the AVREF pin. Thus, it is necessary to cut the current to decrease the power consumption of the whole system. The P21 pin has a more improved driving capacity than any other port and so can directly supply a voltage to the AVREF pin. However, in this case, the actual AVREF voltage have no accuracy. Thus, the conversion value itself has no accuracy and can only be used for relative comparison. In the standby mode, power consumption can be decreased by generating a low level to P21. The AVDD pin should be set to the same voltage as VDD in the standby mode. Fig. 4-65 AVREF Pin Processing in Standby Mode
VDD
P21
P-ch Large
AVREF AVREF. VDD AVREF = VDD .
PD75237
AV ss
117
PD75237
(7)
Others and operating precautions (a) AN0 to AN7 input range
Use AN0 to AN7 input voltages in the specified range. If a voltage larger than VDD or smaller than VSS is input (if in the absolute maximum range), the conversion value of the channel becomes undefined and may affect the conversion values of other channels.
5
(b)
Countermeasures against noise To maintain 8-bit accuracy, extra attention must be paid to noise in the AVREF and AN0 to AN7 pins. The higher the analog input source output impedance becomes the more the noise effect becomes. To prevent that from occurring, mount C externally as shown in Fig. 4-66. Fig. 4-66 Analog Input Pin Processing
VDD
If noise larger than VDD or smaller than VSS may be generated, clamp with a diode having a small VF (0.3 V or less).
AVREF AN0 - AN7 C = 100 - 1000pF
PD75237
VDD VDD AV DD AV SS VSS
(c)
AN4/P90 to AN7/P93 pins
Analog inputs AN4 to AN7 also serve as the input port (PORT9) pin. Do not execute a PORT9 input instruction during A/D conversion with any one of AN4 to AN7 selected. The conversion accuracy may be deteriorated. If a digital pulse is applied to a pin contiguous to the pin undergoing A/D conversion, the expected A/ D conversion value may not be obtained because of coupling noise. Thus, do not apply pulses to such pins.
5
(d)
AVDD pin AVDD pin should be set to the same voltage even when A/D converter is not used, or in standby mode.
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PD75237
4.11 BIT SEQUENTIAL BUFFER : 16 BITS The bit sequential buffer (BSB0 to BSB3) is a special data memory for bit manipulation. Since this buffer can easily carry out bit manipulation by sequentially changing address and bit specification, it is useful to process data having long bit lengths in bit units. This data memory consists of 16 bits and can execute the pmem.@L addressing of bit manipulation instructions. Thus, it can indirectly specify bits with the L register. In this case, processing can be carried out by sequentially shifting the specified bit by simply incrementing/decrementing the L register in the program loop. Fig. 4-67 Bit Sequential Buffer Format
Address Bit Symbol 3 FC3H 2 1 0 3 FC2H 2 1 0 3 2 FC1H 1 BSB1 0 3 FC0H 2 1 0
BSB3
BSB2
BSB0
L Register
L=F
L=C L=B
L=8 L=7
L=4 L=3 DECS L
L=0
INCS L
Remarks
In pmem.@L addressing, the specified bit shifts in accordance with the L register. The bit sequential buffer can be operated irrespective of MBE or MBS specification.
Data manipulation is also possible by direct addressing. 1-, 4- and 8-bit direct addressing can be combined with pmem.@L addressing for applications to continuous 1-bit data input/output. In the case of 8-bit manipulation, the most and least significant 8 bits each are manipulated by specifying BSB0 and BSB2, respectively. 4.12 FIP CONTROLLER/DRIVER (1) FIP controller/driver configuration The PD75237 incorporates a display controller which automatically generates the digit and segment signals by reading the display data memory contents by carrying out DMA operation and a high-voltage output buffer which can directly drive the fluorescent display tube (FIP). The FIP controller/driver configuration is shown in Fig. 4-68. Note The FIP controller/driver can only operate at high and intermediate speeds (PCC = 0011B or 0010B) of the main system clock (SCC.0 = "0"). It may malfunction with any other clock or in the standby mode. Thus, be sure to stop FIP controller operation (DSPM.3 = "0") and then shift the unit to any other clock mode or the standby mode.
119
120 Fig. 4-68 FIP Controller/Driver Block Diagram
Internal Bus 8 Static Mode Register B 4/8 4/8 4 Display Mode Register 4 Digit Select Register 4 Dimmer Select Register Key Scan Flag (KSF) 8 Static Mode Register A Display Data Memory (32 x 4 Bits) Key Scan Register (KS2) 8 Segment Data Latch (8) Display Data Memory (64 x 4 Bits) Key Scan Registers (KS0, KS1) 12 Segment Data Latch (16) Port H 4 Digit Signal Generator 4 4 INTKS IRQKS Set Signal Key Scan Flag (KSF) Selector 8 10 22 4 4 Selector 2 High-Voltage Output Buffer 8 S16/P100S23/P113 10 S0/P120S9/P141 4 10 High-Voltage Output Buffer 2 S10/T15/P142S11/T14/P143 4 S12/T13/P150/PH0S15/T10/P153/PH3 10 T0-T9 VLOAD
PD75237
PD75237
(2)
FIP controller/driver functions The FIP controller/driver built in the PD75237 has the following functions: (a) Segment signal output (DMA operation) and automatic digit signal output are possible by automatic read of display data. (b) The FIP with 9 to 24 segments and 9 to 16 digits (up to a total of 34 display outputs) can be controlled using the display mode register (DSPM), digit select register (DIGS), static mode register A (STATA) and static mode register B (STATB). (c) Output not used for dynamic display can be used for static output or output port. (d) 8 brightness levels can be adjusted using the dimmer function. (e) Hardware is incorporated for key scan application. * Key scan interrupt (IRQKS) generation (key scan timing detection) * Key scan data output from segment output is possible with the key scan buffers (KS0, KS1 and KS2). (f) High-voltage output pin (40 V) capable of directly driving FIP. * Segment output pins (S0 to S9, S16 to S23) : VOD = 40 V, IOD= 3 mA * Digit output pins (T0 to T15) : VOD = 40 V, IOD = 15 mA (g) Display output pin mask option * T0 to T9 and S0 to S15 can incorporate a pull-down resistor in bit units to VLOAD. * S16 to S23 can incorporate a pull-down resistor in bit units to VLOAD or VSS. Determine in 8-bit units whether a pull-down resistor should be incorporated to VLOAD or VSS.
(3)
Display output function differences between PD75237 and PD75216A/PD75217 Table 4-8 shows display output function differences between PD75237 and PD75216A/PD75217. Table 4-8 Display Output Function Differences between PD75237 and PD75216A/PD75217
PD75237
High-voltage output display FIP output total : 34 outputs Segment output : 9 to 24 outputs Digit output Display data area Output dual-function pin Key scan register 1A0H to 1FFH S0 to S23 (PORT10 to PORT15) KS0 to KS2 : 9 to 16 outputs
PD75216A, 75217
FIP output total : 26 outputs Segment output : 9 to 16 outputs Digit output 1C0H to 1FFH S12 to S15 (PORTH) KS0, KS1 : 9 to 16 outputs
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PD75237
Fig. 4-69 FIP Controller Operation Timing
TCYT TDSP T0 TKS
T1 T2
TDIG
TN
Key Scan Flag (KSF) Changeable any time Segment Data
1 Display Cycle
Key Scan Timing
IRQKS Generation
N
: Digit select register set value
TDSP : 1 display cycle 2048 1024 = 341 s: at 6.0 MHz operation*2 = 171 s: at 6.0 MHz operation*1 or fX fX TCYT : Display period (TCYT = TDSP x (N + 2)) TDIG : Digit signal pulse width variable at 8 levels using a dimmer select register
* 1. 2.
244 s at 4.19 MHz operation 489 s at 4.19 MHz operation
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PD75237
(4)
Display mode register (DSPM) The display mode register (DSPM) is a 4-bit register to enable/disable display operation and to specify the number of display segments. Its format is shown in Fig. 4-70. The display mode register is set by the 4-bit memory manipulation instruction. When setting the standby mode (STOP mode, HALT mode) or operating the DSPM with the subsystem clock (fXT), stop the display operation by presetting DSPM.3 to "0". RESET input clears all bits to "0". Fig. 4-70 Display Mode Register Format
Address F88H 3 2 1 0 Symbol DSPM
DSPM3 DSPM2 DSPM1 DSPM0
Display Segment Number Specify Bit
DSPM2 DSPM1 DSPM0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Number of Display Segments 9 segments (+ 8 segments) 10 segments (+ 8 segments) 11 segments (+ 8 segments) 12 segments (+ 8 segments) 13 segments (+ 8 segments) 14 segments (+ 8 segments) 15 segments (+ 8 segments) 16 segments (+ 8 segments)
Remarks
Values when S16 to S23 are set to the dynamic mode by STATB are in parentheses.
Display Operation Enable/Disable Bit
0 DSPM3 1 Display stopped Display enabled
(5)
Digit select register (DIGS)
The digit select register (DIGS) is a 4-bit register to specify the number of digits to be displayed. Its format is shown in Fig. 4-71. DIGS is set by the 4-bit memory manipulation instruction. The number of digits to be displayed can be set in the range from 9 to 16 by DIGS setting. The value of 8-digit or less cannot be selected. RESET input initializes DIGS to "1000B" and selects 9-digit display. Fig. 4-71 Digit Select Register Format
Address F8AH 3 DIGS3 2 DIGS2 1 DIGS1 0 DIGS0 Symbol DIGS
Note
0 to 7 cannot be set in N.
DIGS0 to 3 Set Value N ( = 8 to 15) No. of Digits to be Displayed N+1
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PD75237
(6)
Dimmer select register (DIMS) The dimmer select register (DIMS) is a 4-bit register to specify the digit signal cut width to prevent display light emission from leaking and to maintain the dimmer (brightness adjustment) function. It is also used to select the display cycle (TDSP). The DIMS format is shown in Fig. 4-72. The DIMS is set by the 4-bit memory manipulation instruction. The display cycle of 341 s: at 6.0 MHz operation*1 is normally selected with DIMS.0 set to "1" to minimize light emission leakage. Because if the number of digits to be displayed increases, the display period becomes equivalent to the commercial power supply frequency and display flickers, select 171 s: at 6.0 MHZ operation*2. If any light emission leakage occurs, adjust the digit signal cut width with DIMS.1 to DIMS.3. RESET input clears all bits to "0".
* 1. 2.
489 s at 4.19 MHz operation 244 s at 4.19 MHz operation Fig. 4-72 Dimmer Select Register Format
Address F89H DIMS3 DIMS2 DIMS1 DIMS0
Symbol DIMS
Display Cycle Specify Bit
0 DIMS0 1 Sets 2048 as one display cycle (1 cycle = 341 s:6.0 MHz)*2 fX Sets 1024 as one display cycle (1 cycle = 171 s:6.0 MHz)*1 fX
Digit Signal Cut Width Specify Bit
DIMS3 0 0 0 0 1 1 1 1 DIMS2 0 0 1 1 0 0 1 1 DIMS1 0 1 0 1 0 1 0 1 Digit Signal Cut Width 1/16 2/16 4/16 6/16 8/16 10/16 12/16 14/16
* 1. 2.
244 s at 4.19 MHz operation 489 s at 4.19 MHz operation
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PD75237
(7)
Static mode register The static mode register is intended to specify the static output/dynamic output of the segment output pin. There are two types of static mode registers: static mode register A, static mode register B. Figs. 4-73 and
4-74 show their formats, respectively. These two types of static mode registers are set by an 8-bit manipulation instruction. RESET input clears all bits to "0". (a) Static mode register A (STATA) Static mode register A (STATA) is intended to specify the static output/dynamic output of the S0/P120 to S15/P153/T10/PH3 pins.
Fig. 4-73 Static Mode Register A (STATA)
Address FD6H
7 0
6 0
5 0
4 0
3
2
1
0
Symbol STATA
STATA3 STATA2 STATA1 STATA0
S0 to S15 Pin Stactic Output/Dynamic Output Select Bit
STATA3 STATA2 STATA1 STATA0 S0 to S15 Pins Output Status S0 to S15 become dynamic output. The numbers of segments and digits are set by DSPM and DIGS. S0 to S15 become static output. Perform static data output using an output instruction for ports 12 to 15. These pins are not affected by the DSPM.3 value.
0
0
0
0
1
1
1
1
Note
It is not possible to set some of the S0 to S15 pins to dynamic output and the remaining pins to static output.
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PD75237
(b)
Static mode register B (STATB) Static mode register B (STATB) is intended to specify the static output/dynamic output of the S16/P100 to S23/P113 pins. Fig. 4-74 Static Mode Register B (STATB)
Address FD4H
7 0
6 0
5
4
3 0
2 0
1 0
0 0
Symbol STATB
STATB5 STATB4
S16 to S23 Pin Static Output/Dynamic Output Select Bit
STATB5 0 STATB4 0 S16 to S23 Pins Output Status Dynamic output. Dynamic output is generated in accordance with 1A0H to 1BDH contents. Static output. Perform static data output using an output instruction for ports 10 and 11. These pins are not affected by the DSPM.3 value.
1
1
Note
It is not possible to set some of the S16 to S23 pins to dynamic output and the remaining pins to static output.
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PD75237
(8)
Display mode selection The numbers of segments and digits which can be displayed using the built-in FIP controller/driver depend on the display mode. Fig. 4-75 shows a display mode selection diagram. Fig. 4-75 Display Mode Selection Diagram
Digit Number Selection 0 9 10 11 12 13 14 15 16
9-Segment Mode 9 10-Segment Mode 10 11-Segment Mode 11 12-Segment Mode 12 13-Segment Mode 13 14-Segment Mode 14
Segment Number Selection
15-Segment Mode 15 16-Segment Mode 16 17-Segment Mode 17 18-Segment Mode 18 19-Segment Mode 19 20-Segment Mode 20 21-Segment Mode 21 22-Segment Mode 22 23-Segment Mode 23 24-Segment Mode 24
Remarks
The circled modes with shading are those expanded from the PD75216A and PD75217.
127
PD75237
(9)
Display data memory The display data memory is an area storing the displayed segment data and is mapped at addresses 1A0H to 1FFH of the data memory. Display data is automatically read by a display controller (DMA operation). The areas not used for display can be used as normal data memory. Display data operation is carried out by a data memory manipulation instruction. Data manipulation is possible in 1-, 4- and 8-bit units. Only even addressed can be specified for 8-bit manipulation instruction execution. Addresses 1FCH to 1FFH, 1BEH and 1BFH of the display data memory also serve as key scan registers (KS0, KS1 and KS2). Table 4-9 Data Memories which also Serve as Key Scan Registers
Key Scan Register KS0 KS1 KS2
Data Memory which also Serves as Key Scan Register 1FCH, 1FDH 1FEH, 1FFH 1BEH, 1BFH
Note
Extra caution is necessary when transferring a program developed for the PD75237 to one for the
PD75216A and PD75217 because a maximum of 16 segments are displayed and no data memory is incorporated at addresses (1A0H + 4n and 1A1H + 4n) in the case of the PD75216A and PD75217.
128
PD75237
Fig. 4-76 Display Data Memory Contents and Segment Outputs
24-Segment Mode 23-Segment Mode 22-Segment Mode 21-Segment Mode 20-Segment Mode 19-Segment Mode 18-Segment Mode 17-Segment Mode 16-Segment Mode 15-Segment Mode 14-Segment Mode 13-Segment Mode 12-Segment Mode 11-Segment Mode 10-Segment Mode 9-Segment Mode 3 1A1H 1A3H 1A5H 1A7H 1A9H 1ABH
Display Data Memory
Bit
03 1A0H 1A2H 1A4H 1A6H 1A8H 1AAH 1ACH 1AEH 1B0H 1B2H 1B4H 1B6H 1B8H 1BAH 1BCH 1BEH(KS2)
03 1C3H 1C7H 1CBH 1CFH 1D3H 1D7H 1DBH 1DFH 1E3H 1E7H 1EBH 1EFH 1F3H 1F7H 1FBH 1FFH
03 1C2H 1C6H 1CAH 1CEH 1D2H 1D6H 1DAH 1DEH 1E2H 1E6H 1EAH 1EEH 1F2H 1F6H 1FAH 1FEH(KS1)
03 1C1H 1C5H 1C9H 1CDH 1D1H 1D5H 1D9H 1DDH 1E1H 1E5H 1E9H 1EDH 1F1H 1F5H 1F9H 1FDH
03 1C0H 1C4H 1C8H 1CCH 1D0H 1D4H 1D8H 1DCH 1E0H 1E4H 1E8H 1ECH 1F0H 1F4H 1F8H 1FCH(KS0)
0 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 Timing Output
1ADH 1AFH 1B1H 1B3H 1B5H 1B7H 1B9H 1BBH 1BDH 1BFH
Key Scan Data
KS2
KS1
KS0
Tks
Segment S23S22 S21 S20 S19S18 S17 S16 S15S14 S13 S12 S11S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Output Timing Output Port H Output
T10T11 T12 T13 T14 T15
(When specified by digit select register)
PH3PH2PH1PH0
(When none of segment output and timing output are used)
129
PD75237
(10) Key scan registers (KS0, KS1 and KS2) The key scan registers (KS0, KS1 and KS2) are used to set the segment output data in the key scan timing mapped in the part of the display data memory (addresses 1FCH, 1FDH, 1FEH, 1FFH, 1BEH and 1BFH). KS0, KS1 and KS2 are 8-bit registers and are normally manipulated by an 8-bit manipulation instruction (the lower 4 bits can be manipulated bit-wise or in 4-bit units). Data set to KS0, KS1 and KS2 is output from the segment output pin at the key scan timing. During the key scan timing the segment output data can be immediately changed by rewriting KS0, KS1 and KS2. Key scan can be performed using the segment output. (11) Key scan flag (KSF) The key scan flag is set ("1") during the key scan timing and is automatically reset ("0") in all other timings. The KSF is mapped at bit 3 of address F8AH and is bit-wise testable. No write is possible. Whether the KSP is at the key scan timing can be checked by testing it. Thus, it is possible to check whether key input data is correct or not.
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PD75237
5. INTERRUPT FUNCTIONS
The PD75237 has eight types of interrupt sources and can generate multiple interrupts with priority order. It is also equipped with two types of test sources. INT2 is an edge detected testable input.
Table 5-1 Interrupt Source Types
Interrupt Source
Internal/ External Internal
Interrupt Order *1
Vectored Interrupt Request Signal (Vector Table Address)
INTBT (Reference timer interval signal from the basic interval timer)
1 INT4 (Rising or falling edge detection) INT0 (Rising and falling detected edge selection) INT1 INTCSI0 (Serial data transfer end signal) INTT0 (Match signal from timer event/counter 0) INTTPG (Match signal from timer/pulse generator) INTKS (Key scan timing signal from display controller) INT2 *2 (Rising edge detection) INTW *2 (Signal from watch timer) External Internal Internal Internal Internal External 3 4 5 6 7 External External 2
VRQ1 (0002H) VRQ2 (0004H) VRQ3 (0006H) VRQ4 (0008H) VRQ5 (000AH) VRQ6 (000CH) VRQ7 (000EH)
Testable input signal (IRQ2 and IRQW set) Internal
* 1. 2.
Interrupt order is priority order to be applied when two or more interrupt requests are generated simultaneously. These are test sources. They are affected by interrupt enable flags as in the case of interrupt sources, but no vectored interrupt is generated. The PD75237 interrupt control circuit has the following functions: (a) Hardware-controller vectored interrupt function which can control interrupt acknowledge with the interrupt enable flag (IExxx) and the interrupt master enable flag (IME). (b) Function of setting any interrupt start address. (c) Multiple interrupt function which can specify priority order with the interrupt priority select register (IPS). (d) Interrupt request flag (IRQxxx) test function. (Interrupt generation can be checked by software.) (e) Standby mode release function. (Interrupt to be released by interrupt enable flag can be selected.)
5.1
INTERRUPT CONTROL CIRCUIT CONFIGURATION
The interrupt control circuit has a configuration shown in Fig. 5-1 and each hardware is mapped in the data memory space.
131
132 Fig. 5-1 Interrupt Control Circuit Block Diagram
Internal Bus 2 IM1 2 IM0 Interrupt Enable Flag (IExxx) (IME) 4 IPS 2 IST Noise Eliminator INT4 /P00 INT0 /P10 INT1 /P11 INT BT Both Edge Detector Edge Detector Edge Detector INTCSI0 Decoder IRQBT VRQn IRQ4 IRQ0
Vector Table Address Generator
IRQ1
IRQCSI0
Priority Control Circuit
INTT0
IRQT0
INTTPG INTKS
IRQTPG
IRQKS Standby Release Signal
INTW INT2 /P12 Rising Edge Detector
IRQW
PD75237
IRQ2
PD75237
5.2 (1)
INTERRUPT CONTROL CIRCUIT HARDWARE DEVICES Interrupt request flag, interrupt enable flag There are ten interrupt request flags (IRQxxx) corresponding to interrupt sources (interrupt :8, test :2) as 5
shown below. INT0 interrupt request flag (IRQ0) INT1 interrupt request flag (IRQ1) INT2 interrupt request flag (IRQ2) INT4 interrupt request flag (IRQ4) BT interrupt request flag (IRQBT) Serial interface interrupt request flag (IRQCSI0) Timer/event counter interrupt request flag (IRQT0) Timer/pulse generator interrupt request flag (IRQTPG) Key scan interrupt request flag (IRQKS) Watch timer interrupt request flag (IRQW)
Interrupt request flag is set to "1" at generation of an interrupt request and is automatically cleared ("0") upon execution of interrupt service. IRQBT and IRQ4 carry out clear operation differently because they share the vector address. (See 5.5 VECTOR ADDRESS SHARING INTERRUPT SERVICING.) 5 There are ten interrupt enable flags (IExxx) corresponding to interrupt request flags as shown below. INT0 interrupt enable flag (IE0) INT1 interrupt enable flag (IE1) INT2 interrupt enable flag (IE2) INT4 interrupt enable flag (IE4) BT interrupt enable flag (IEBT) Serial interface interrupt enable flag (IECSI0) Timer/event counter interrupt enable flag (IET0) Timer/pulse generator interrupt enable flag (IETPG) Key scan interrupt enable flag (IEKS) Watch timer interrupt enable flag (IEW)
When the contents of interrupt enable flag is "1", interrupt is enabled and when it is "0", interrupt is disabled. When the interrupt request flag is set and the interrupt enable flag has enabled interrupt, the vectored interrupt request (VRQn) is generated. This signal is also used to release the standby mode. Both the interrupt request flag and interrupt enable flag are operated by the bit manipulation instruction and 4-bit memory manipulation instruction. They can be operated directly by the bit manipulation instruction irrespective of MBE setting. The interrupt enable flag is operated by the EI IExxx and DI IExxx instruction. The SKTCLR instruction is normally used to test the interrupt request flag. When the interrupt request flag is set by an instruction even if an interrupt has not been generated, the vectored interrupt is executed in the same way as when an interrupt had been generated. RESET input clears the interrupt request flag and the interrupt enable flag ("0") and disables all interrupts.
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Table 5-2 Interrupt Request Flag Set Signals
Interrupt Request Flag IRQBT IRQ4 IRQ0 Interrupt Enable Flag IEBT IE4 IE0
Interrupt Request Flag Set Signal
Set by the reference time interval signal generated by the basic interval timer. Set upon detection of the rising or falling edge of the INT4/P00 input signal. Set upon detection of the INT0/P10 pin input signal edge. The detected edge is selected using the INT0 mode register (IM0). Set upon detection of the INT1/P11 pin input signal edge. The detected edge is selected using the INT1 mode register (IM1). Set by the serial data transfer operation end signal of the serial interface. Set by the match signal from the timer/event counter #0. Set by the match signal from the timer/pulse generator. Set by the key scan timing signal from the display controller. Set by a signal from the watch timer. Set upon detection of the rising edge of the INT2/P12 pin input signal.
IRQ1 IRQCSI0 IRQT0 IRQTPG IRQKS IRQW IRQ2
IE1 IECSI0 IET0 IETPG IEKS IEW IE2
5
(2)
Noise eliminator and edge detection mode register INT0, INT1 and INT2 each have the configuration shown in Figs. 5-2 and 5-3 and serve as the external
interrupt input capable of selecting detected edges. INT0 has a function of eliminating noise with sampling clock. Pulses having a shorter width than 2 sampling clock cycles* are eliminated as noise by noise eliminator. However, pulses having a larger width than 1 sampling clock cycle may be acknowledged as an interrupt signal depending on the sampling timing. Pulses having a larger width than 2 sampling clock cycles are securely acknowledged as an interrupt signal. INT0 has two sampling clocks, and fx/64 and can select and use either clock. Selection is made by bit 3 (IM03) of the edge detection mode register (refer to Fig. 5-4). IRQ2 is set by detecting the rising edge of INT2 pin input. Edge detection mode registers (IM0 and IM1) to select detection edge have the format shown in Fig. 5-4. IM0 and IM1 each are set by a 4-bit memory manipulation instruction. RESET input clears all bits to 0 and specifies INT0, INT1 and INT2 for the rising edge.
* When sampling clock is : 2tCY When sampling clock is fx/64 : 128/fX
Note 1. Since INT0 samples by clock, it is not operated in the standby mode. 2. Pulses are input to the INT0/P10 pin serving as a port via the noise eliminator. Thus, input pulses having two sampling clock cycles or larger.
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Fig. 5-2 INT0 and INT1 Configuration
INT0/ P10
Noise Eliminator
Edge Detector IM01, IM00
INT0 IRQ0 Set Signal
Selector
IM03 fX 64 Edge Detector 2 INT1 IRQ1 Set Signal
INT1/ P11
IM10 Input Buffer IM1 IM0
4 Internal Bus
4
Fig. 5-3 INT2 Configuration
INT2 IRQ2 Set Signal
INT2/P12
Rising Edge Detector
Input Buffer
Internal Bus
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Fig. 5-4 Edge Detection Mode Register Format
Address 3 FB4H IM03 2 0 1 IM01 0 IM00 IM0 Symbol
Detection Edge Specification
0 0 1 1 0 1 0 1 Rising edge specification Falling edge specification Rising and falling edge specification Ignored (interrupt request flag not set)
5
Sampling Clock
0 1
(0.67, 1.33, 2.67, 10.7 s: at 6.0 MHz operation)*1
fx/64 (10.7 s: at 6.0 MHz operation)*2
FB5
0
0
0
IM10
IM1
0 1
Rising edge specification Falling edge specification
* 1. 2. Note
0.95, 1.91, 3.82, 15.3 s at 4.19 MHz operation 15.3 s at 4.19 MHz operation If the edge detection mode register is changed, the interrupt request flag may be set. To prevent that from occurring, disable interrupt and change edge detection mode register first, then enable interruption after clearing the interrupt request flag by the CLR1 instruction. If fx/64 has been selected as sampling clock by changing IM0, it is necessary to clear the interrupt request flag 16 machine cycles after the mode register has been changed.
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(3)
Interrupt priority select register (IPS) The interrupt priority select register is used to select high interrupt enabled for multiple interrupt and is specified by the least significant 3 bits. Bit 3 is an interrupt master enable flag (IME) to specify whether all interrupts should be disabled or not. The IPS is set by the 4-bit memory manipulation instruction and bit 3 is set/reset by the EI/DI instruction. When changing the low-order 3-bit contents of IPS, it is necessary to do so with interrupt disabled (IME = 0). RESET input clears all bits to "0".
Fig. 5-5 Interrupt Priority Select Register
Address 3 FB2H IPS3 2 IPS2 1 IPS1 0 IPS0 IPS Symbol
High Interrupt Select
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 None of interrupts are made high interrupts. VRQ1 (INTBT/INT4) VRQ2 (INT0) VRQ3 (INT1) VRQ4 (INTCSI0) VRQ5 (INTT0) VRQ6 (INTTPG) VRQ7 (INTKS) Vectored interrupts on the left are taken as high interrupts.
Interrupt Mask Enable Flag (IME)
0 All interrupts are disabled and vectored interrupt is not started. Interrupt enable/disable is controlled by the corresponding interrupt enable flag.
1
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5.3
INTERRUPT SEQUENCE If interrupt is generated, it is processed using the following procedure:
Interrupt (INTXXX) generated
IRQXXX set
NO IEXXX set? YES Corresponding VRQn generated NO
Reserved until IEXXX is set
IME = 1 YES Depends on the instruction being executed when IRQn is set. Is VRQn a high interrupt? YES *1 IST 1,0 = 00 or 01 YES
Reserved until IME is set Reserved until termination of operation being executed *1 IST 1,0 = 00 YES If two or more VRQn have been generated simultaneously, one VRQn is selected according to the interrupt order shown in Table 5-1. Selected VRQn Remaining VRQn NO
NO
NO
PC and PSW contents are saved into the stack memory and the data *2 in the vector table corresponding to the started VRQn is set to PC, RBE and MBE.
2 Machine Cycles
IST0 and IST1 contents are changed from 00 to 01 or from 01 to 10.
Acknowledged IRQXXX is reset. (If the interrupt source shares the vector address, refer to 5.5 VECTOR ADDRESS SHARING INTERRUPT SERVICING.)
Interrupt service program processing start
* 1. 2.
IST1 and IST0 : Interrupt status flags (PSW bits 3, 2: Refer to Table 5-3 IST1 and IST0 Interrupt Servicing Statuses). The start address of the interrupt service program and the MBE and RBE set values at the start of interrupt are stored in each vector table.
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PD75237
5.4
MULTI-INTERRUPT SERVICE CONTROL The following two methods are available for the PD75237 to generate multi-interrupts.
(1)
Multi-interruption specifying high interrupt
This is a standard multi-interrupt method of the PD75237 in which one interrupt source is selected and multi-interruption (dual interrupt) is enabled. In other words, the high interrupt specified using the interrupt priority select register (IPS) is enabled when the status of the operation being executed is 0 or 1. All other interrupts (low interrupts) are only enabled when the status is 0. (Refer to Fig. 5-6 and Table 5-3.)
Fig. 5-6 Multi-Interruption by High Interrupt
Normal Processing (Status 0) Interrupt Disable IPS Set Interrupt Enable Low or High Interrupt Servicing (Status 1) High Interrupt Servicing (Status 2)
Low or High Interrupt Generated
High Interrupt Generated
Table 5-3 IST1 and IST0 Interrupt Servicing Statuses
Status of Servicing being Executed CPU Processing Contents Normal program being processed Low or high interrupt being servicing High interrupt being servicing Interrupt Acknowledgeable Interrupt Request After Interrupt Acknowledgement IST1 IST0
IST1
IST0
0
0
Status 0
All interrupts acknowledgeable
0
1
0
1
Status 1
Only high interrupt acknowledgeable
1
0
1
0
Status 2
All interrupts not acknowledgeable
-
-
1
1
Setting prohibited
When an interrupt is acknowledged, IST1 and IST0 are saved into the stack memory together with other PSW and is changed to a status higher by one level. When RET1 instruction is executed, the original IST1 and IST0 values are reset.
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(2)
Multi-interruption changing the interrupt status flag As is clear from Table 5-3, multi-interrupt is enabled by changing the interrupt status flag using the program. That is, multi-interrupt is enabled by changing IST1 and IST0 each to "0" using the interrupt servicing program and setting status 0. This method is used to enable multi-interrupt with two to more interrupts or multi-interruption with triple or more interrupts. Before changing IST1 and IST0, disable interruption by DI instruction.
Fig. 5-7 Multi-Interruption by Changing the Interrupt Status Flag
Normal Processing (Status 0) Interrupt Disable IPS Set Interrupt Enable
Single Interrupt
Dual Interrupt
Triple Interrupt
Interrupt Disable IST Change Interrupt Enable
Status 1
Low or High Interrupt Generated
Status 0 Low or High Interrupt Generated
Status 1
High Interrupt Generated Status 0
Status 2
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PD75237
5.5
VECTOR ADDRESS SHARING INTERRUPT SERVICING
Since the INTBT and INT4 interrupt sources share the vector table, interrupt source selection is carried out as follows: (1) When only one interrupt source is used Among the two interrupt sources sharing the vector table, set the interrupt enable flag of the necessary interrupt source ("1") and clear the other interrupt enable flag ("0"). In this case, an interrupt request is generated by the enabled interrupt source (IExxx=1). When the request is acknowledged, the corresponding interrupt request flag is reset (as is the case with an interrupt not sharing the vector address). (2) When both interrupt sources are used Set the interrupt enable flags corresponding to the two interrupt sources ("1"). In this case, the logical sum
of the interrupt request flags of the two interrupt sources becomes an interrupt request. And, if an interrupt request by the setting of one or both interrupt request flags is acknowledged, none of the interrupt request flag is reset. Accordingly, it is necessary to check in the interrupt service routing by which interrupt source the interrupt has been generated. It can be done by executing the DI instruction at the beginning of the interrupt service routine and checking the interrupt request flag by the SKTCLR instruction.
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PD75237
6. STANDBY FUNCTIONS
Two standby modes (STOP mode and HALT mode) are available for the PD75237 to decrease power consumption in the program standby mode. 6.1 STANDBY MODE SETTING AND OPERATING STATE Table 6-1 Operation Status in Standby Mode
STOP Mode Set instruction System clock when set STOP instruction Setting enabled only with main system clock. Oscillator stops only with main system clock. Operation enabled only when external SCK0 input is selected for serial clock. Operation enabled only when external SCK1 input is selected for serial clock. Operation stopped. Operation enabled only when TI0 pin input is specified for count clock.
HALT Mode HALT instruction Setting enabled with either main system clock or subsystem clock. Stops only with CPU clock (Oscillation continued). Operation enabled when the main system clock oscillates or with external SCK0. Operation enabled only when the main system clock oscillates. Operation (IRQBT set at reference time intervals). Operation enabled.
Clock oscillator
Serial interface (channel 0)
Serial interface (channel 1)
Basic interval timer Operating State
Timer/event counter
Watch timer
Operation enabled only fXT is selected for Operation enabled. count clock. Operation stopped. Operation enabled only when the main system clock oscillates. Operation enabled only when the main system clock oscillates. Operation enabled only when the main system clock oscillates.
Timer/pulse generator
Event counter
Operation stopped.
A/D converter FIP controller/driver External interrupt CPU Release signal
Operation stopped.
Operation disabled (display off mode set before disabling). INT0 operation disabled. INT1, INT2 and INT4 operation enabled. Operation stopped. Interrupt request signal or RESET input from operational hardware enabled by interrupt enable flag.
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PD75237
The STOP and HALT modes are set by STOP and HALT instructions, respectively. (The two instructions are instructions to set PCC bit 3 and bit 2, respectively.) When changing the CPU operation clock with the least significant 2 bits of PCC, a delay may result from PCC rewrite to CPU clock change as shown in Table 4-1. Thus, when changing the operation clock before the standby mode is set or the CPU clock after the standby mode is released, set the standby mode after the passage of the machine cycle required for CPU clock change following PCC rewrite. In the standby mode, the data of all registers and data memories which stop operating is held. Such units include general registers, flag, mode registers and output latches. Note 1. When the STOP mode is set, X1 input is internally short-circuited to VSS (GND potential) to prevent leakage from the crystal resonator unit. Thus, the use of STOP mode is prohibited in a system using external clocks. Because the interrupt request signal is used to release the standby mode, the standby mode is immediately released if there is an interrupt source with both the interrupt request flag and interrupt enable flag set. Thus, the STOP mode is set to the HALT mode just after STOP instruction execution. After waiting for the time period set by the BTM register, the operating mode is reset.
2.
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PD75237
6.2
STANDBY MODE RELEASE
The STOP and HALT modes each are released upon generation of the interrupt request signal* enabled by the interrupt enable flag or by RESET input. Fig. 6-1 shows release operation in each mode. * Except INT0 to INT2. Fig. 6-1 Standby Mode Release Operation (1/2)
(a)
Release by RESET input in STOP mode
Wait (Approx. 21.8 ms : 6.0 MHz) *
STOP Instruction
RESET Signal Operating Mode Oscillation Clock STOP Mode Oscillation Stop HALT Mode Oscillation Operating Mode
(b)
Release by interrupt generation in STOP mode
Wait (time set by BTM)
STOP Instruction
Standby Release Signal Operating Mode Oscillation STOP Mode Oscillation Stop HALT Mode Oscillation Operating Mode
Clock
Remarks
The broken line shows the case in which the interrupt request which released the standby mode has been acknowledged (IME = 1). Release by RESET input in HALT mode
Wait (Approx. 21.8 ms : 6.0 MHz) *
(c)
HALT Instruction
RESET Signal Operating Mode HALT Mode Oscillation Operating Mode
Clock
* 144
31.3 ms at 4.19 MHz operation
PD75237
Fig. 6-1 Standby Mode Release Operation (2/2) (d) Release by interrupt generation in HALT mode
HALT Instruction Standby Release Signal Operating Mode HALT Mode Oscillation Operating Mode
Clock
Remarks
The broken line shows the case in which the interrupt request which released the standby mode has been acknowledged (IME = 1). The wait time upon STOP mode release does not include a time from STOP mode release to clock oscillation start ("a" below) whether the STOP mode is released by RESET input or interrupt generation.
STOP Mode Release X1 in Voltage Waveform a Vss
If the STOP mode has been released by interrupt generation, the wait time is determined by BTM setting. (Refer to Table 6-2.) Table 6-2 Wait Time Selection by BTM (When fX = 6.0 MHz)
BTM3 - - - - BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 0 1 1 1 Wait Time* (Values at fX = 6.0 MHz are shown in parentheses) Approx. 220/fX (approx. 175 ms) Approx. 217/fX (approx. 21.8 ms) Approx. 215/fX (approx. 5.46 ms) Approx. 213/fX (approx. 1.37 ms) Setting prohibited
In all other cases
(When fX = 4.19 MHz)
BTM3 - - - - BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 0 1 1 1 Wait Time* (Values at fX = 4.19 MHz are shown in parentheses) Approx. 220/fX (approx. 250 ms) Approx. 217/fX (approx. 31.3 ms) Approx. 215/fX (approx. 7.82 ms) Approx. 213/fX (approx. 1.95 ms) Setting prohibited
In all other cases
*
Wait time does not include a time from STOP mode release to oscillation start.
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PD75237
6.3 (1) (2)
OPERATION AFTER STANDBY MODE RELEASE If the STOP mode has been released by RESET input, normal reset operation is carried out. If the STOP mode has been released by interrupt generation, the bit 3 (IME) contents of the IPS determine
whether a vectored interrupt should be executed when the CPU resumes instruction execution. (a) When IME = "0" Execution is resumed with the instruction (NOP instruction) following standby mode setting after the standby mode has been released. The interrupt request flag is held. When IME = "1" Vectored interrupt is executed following execution of two instructions after the standby mode has been released. If the standby mode has been released by INTW (testable input), no vectored interrupt is generated; so the same processing as with (a) is carried out.
(b)
146
PD75237
7. RESET FUNCTIONS
The reset signal (RES) generator has a configuration shown in Fig. 7-1. Fig. 7-1 Reset Signal Generator
RESET
Interrupt Reset Signal (RES)
Reset operation is shown in Fig. 7-2. The output buffer is turned OFF upon RESET input. Table 7-1 shows each hardware status after reset. Fig. 7-2 Reset Operation by RESET input
Wait (21.8 ms : 6.0 MHz) *
RESET Input
Operating Mode or Standby Mode
HALT Mode
Operating Mode
Internal Reset Operation
*
31.3 ms at 4.19 MHz operation
Table 7-1 shows each hardware status after reset.
147
PD75237
Table 7-1 Hardware Statuses after Reset (1/2)
Hardware
RESET Input in Standby Mode Sets the low-order 6 bits of program memory address 0000H to PC13-8 and the contents of address 0001H to PC7-0. Hold 0 0 Sets bit 6 of program memory address 0000H to RBE and bit 7 to MBE. Hold Hold 0, 0 Undefined Undefined Undefined 0 0 FFH 0 0,0 0 Hold 0 0 0 0 Hold 0 0 Hold 1 Hold 0 0
RESET Input in Operation
Program counter (PC)
Carry flag (CY) Skip flag (SK0-SK2) PSW Interrupt status flag (IST1, IST2) Bank enable flags (MBE, RBE) Data memory (RAM) General registers (X, A, H, L, D, E, B, C) Bank select registers (MBS, RBS) Stack pointer (SP) Stack bank select register (SBS) Basic interval timer Counter (BT) Mode register (BTM) Counter (T0) Timer/event counter Modulo register (TMOD0) Mode register (TM0) TOE0, TOUT F/F Watch timer Timer/pulse generator Mode register (WM) Modulo register (MODH, MODL) Mode registet (TPGM) Counter (T1) Event counter Mode register (TM1) Gate control register (GATEC) Shift register (SIO0) Serial interface (channel 0) Operating mode register (CSIM0) SBI control register (SBIC) Slave address register (SVA) P01/SCK0 output latch Shift register (SIO1) Serial interface (channel 1) Operating mode register (CSIM1) Serial transfer end flag (EOT)
Undefined 0 0
Undefined Undefined 0, 0 Undefined Undefined Undefined 0 0 FFH 0 0, 0 0 Hold 0 0 0 0 Undefined 0 0 Undefined 1 Undefined 0 0
148
PD75237
Table 7-1 Hardware Statuses after Reset (2/2)
Hardware Mode register (ADM), EOC A/D converter SA register Bit sequential buffer (BSB0 to BSB3) Mode register (DSPM) Dimmer select register (DIMS) FIP controller/ driver Digit select register (DIGS) Display data memory Output buffer Static mode register (STATA, STATB) Clock generator and clock output circuit Processor clock control register (PCC) System clock control register (SCC) Clock output mode register (CLOM) Interrupt request flag (IRQxxx) Interrupt function Interrupt enable flag (IExxx) Interrupt master enable flag (IME) INT0 and INT1 mode registers (IM0, IM1) Output buffer (ports 2 to 7) Output latch (ports 2 to 7) Digital port Input/output mode register (PMGA, PMGB) Pull-up resistor specify register (POGA) Output buffer Ports 10 to 15 Output latch Port H Output latch
RESET Input in Standby Mode 04H (EOC = 1) Undefined Hold 0 0 8H Hold OFF 0, 0 0 0 0 Reset 0 0 0, 0 OFF Clear 0 0 OFF 0 Hold
RESET Input in Operation 04H (EOC = 1) Undefined Undefined 0 0 8H Hold OFF 0, 0 0 0 0 Reset 0 0 0, 0 OFF Clear 0 0 OFF 0 Undefined
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PD75237
8. INSTRUCTION SET
8.1 (1) CHARACTERISTIC INSTRUCTIONS OF PD75237 GETI instruction The GETI instruction is a 1-byte instruction to execute the following three types of operations by referring to the 2-byte table in the program memory. It can considerably help to decrease the number of program steps. (a) (b) (c) (d) Subroutine call to 16K-byte space (0000H to 3FFFH) of table data as call instruction call address. Branch to 16K-byte space (0000H to 3FFFH) of table data as branch instruction branch address Execution of table data as 2-byte instruction (except BRCB and CALLF instructions) Execution of table data as 1-byte instruction and 2 operation codes.
As shown in Fig. 3-2, the table addressed referred to by GETI instruction as 0020H to 007FH of the program memory and data can be set in 48 tables. When describing table addresses as operands, describe even addresses. Note 1. 2-byte instructions which can be referred to by GETI instruction are limited to 2-machine cycle instructions. 2. When referring to two 1-byte instructions by GETI instruction, combinations are limited as follows.
1st Byte Instruction
2nd Byte Instruction INCS DECS INCS DECS INCS INCS DECS INCS DECS INCS INCS DECS INCS DECS L L H H HL E E D D DE L L D D
MOV MOV XCH
A, @HL @HL, A A, @HL
MOV XCH
A, @DE A, @DE
MOV XCH
A, @DL A, @DL
3. When a branch instruction or subroutine instruction is referenced by a GETI instruction, the relevant branch destination or subroutine call address must be within 16K bytes (0000H to 3FFFH). It is not possible to use a GETI instruction to reference a branch instruction or subroutine call instruction to an address outside this range (4000H to 5F7FH).
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PD75237
Since the PC does not increment during execution of GETI instruction, it continues processing with the address following GETI instruction. If an instruction preceding the GETI instruction has the skip function, the GETI instruction is skipped as is the case with all other 1-byte instructions. If the instruction referred to by the GETI instruction has the skip function, an instruction following the GETI instruction is skipped. When instructions having stack effects are referred to by the GETI instruction, the following operations are carried out: * If an instruction preceding GETI instruction also has the stack effects of the same group, the execution of GETI instruction eliminates the stack effects and the instructions referred to are not skipped. * If an instruction following GETI instruction also has the stack effects of the same group, the stack effects derived from the instructions referred to are valid and the following instruction is skipped. (2) Bit manipulation instruction In addition to normal bit manipulation instructions (set and clear instructions), the bit test instruction, bit transfer instruction and bit Boolean instructions (AND, OR, XOR) are available for the PD75237. Manipulation bits are specified by bit manipulation addressing. Three types of available addressing operations and bits manipulated by each addressing are shown below.
Addressing
Specifiable Peripheral Hardware RBE/MBE/IST1, IST0/IExxx/IRQxxx
Specifiable Bit Address Range FB0H to FBFH FF0H to FFFH FC0H to FFFH All manipulatable bits of the memory bank specified by MB
fmem.bit PORT0 to PORT15 pmem.@L @H+mem.bit BSB0 to BSB3, PORT0 to PORT15 All peripheral hardware devices enabled for bit manipulation
Remarks
1. 2.
xxx : 0, 1, 2, 3, 4, BT, T0, TPG, CSI0, KS, W MB = MBE* MBS
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(3)
Stack instructions If the instructions of the same group of the following three instructions are stacked (set at two or more continuous addresses) in the program, the stack instruction placed at the start point is executed. In the subsequent execution, one stack instruction is replaced with one NOP instruction. Group A: MOV A, #n4, Group B: MOV HL, #n8 MOV XA, #n8
(4)
Radix adjustment instructions Radix adjustment instructions to adjust the result of 4-bit data addition or subtraction to any radix is available for the PD75237. When the radix to be adjusted is m. * ADD ADDS A, #16-m ADDC A, @HL ADDS A, #m SUBC A, @HL
* Subtract
ADDS A, #m Using the above combinations, the addition/subtraction result with the memory addressed by the accumulator and register pair HL is adjusted to a m-ary radix. In the case of subtraction, m's complement of the subtraction result is set to the accumulator. The overflow/underflow remains in the carry flag (in these instruction combinations, the "ADDS A, #m" instruction skip function is disabled).
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PD75237
8.2 (1)
INSTRUCTION SET AND OPERATION Operand identifier and description Enter an operand in the operand column of each instruction using the description method relating to the
operand identifier of the instruction (refer to the assembler specifications for details). If more than one description method is available, select one. Capital alphabetic letters, plus and minus signs are keywords. Describe them as they are. In the case of immediate data, describe appropriate numerical values or labels. Symbols in the register and flag format diagrams in chapters 3 to 5 can be described as labels in place of mem, fmem, pmem, bit, etc. (Available labels are limited for fmem and pmem. Refer to 8.1 (2) Bit manipulation instruction.)
Identifier reg reg 1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr1 addr caddr faddr taddr PORTn IExxx RBn MBn X, A, B, C, D, E, H, L X, B, C, D, E, H, L
Description Method
XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label* 2-bit immediate data or label FB0H to FBFH and FF0H to FFFH immediate data or labels FC0H to FFFH immediate data or labels 0000H to 5F7FH immediate data or labels 0000H to 3F7FH immediate data or labels 12-bit immediate data or label 11-bit immediate data or label 20H to 7FH immediate data (bit0 = 0) or label PORT0 to PORT15 IEBT, IECSI0, IET0, IETPG, IE0, IE1, IE2, IEKS, IEW, IE4 RB0 to RB3 MB0, MB1, MB2, MB3, MB15
*
For 8-bit data processing, only even addresses can be specified.
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PD75237
(2)
Legend for operation description A : A register; 4-bit accumulator B : B register C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP SBS CY PSW MBE RBE PORTn IME IPS IExxx RBS MBS PCC * (xx) xxH : : : : : : : : : : : : : : : : : : : : : : : : : : : : C register D register E register H register L register X register Register pair (XA); 8-bit accumulator Register pair (BC) Register pair (DE) Register pair (HL) Expanded register pair (XA') Expanded register pair (BC') Expanded register pair (DE') Expanded register pair (HL') Program counter Stack pointer Stack bank select register Carry flag; Bit accumulator Program status word Memory bank enable flag Register bank enable flag Port n (n = 0 to 15) Interrupt master enable flag Interrupt priority select register Interrupt enable flag Register bank select register Memory bank select register Processor clock control register
: Address and bit delimiter : Contents addressed by xx : Hexadecimal data
154
PD75237
(3)
Description of symbols in the addressing area column
*1
MB = MBE* MBS (MBS = 0, 1, 2, 3, 15) MB = 0 MBE = 0 : MB = 0 (00H to 7FH) MB = 15 (80H to FFH) MBE = 1 : MB = MBS (MBS = 0, 1, 2, 3, 15) MB = 15, fmem = FB0H to FBFH, FF0H to FFFH MB = 15, pmem = FC0H to FFFH addr = 0000H to 3FFFH addr = (Current PC) - 15 to (Current PC) - 1, (Current PC) + 2 to (Current PC) + 16 caddr = 0000H 1000H 2000H 3000H 4000H 5000H to to to to to to 0FFFH 1FFFH 2FFFH 3FFFH 4FFFH 5F7FH (PC14, 13, 12 (PC14, 13, 12 (PC14, 13, 12 (PC14, 13, 12 (PC14, 13, 12 (PC14, 13, 12 = = = = = = 00B) or 01B) or 10B) or 11B) or 100B) or 101B)
*2 *3
Data Memory Addressing
*4
*5 *6 *7
*8
Program Memory Addressing
*9 *10 *11
faddr = 0000H to 07FFH taddr = 0020H to 007FH addr1 = 0000H to 5F7FH
Remarks 1. 2. 3. 4. (4)
MB indicates accessible memory bank. In *2, MB = 0 irrespective of MBE and MBS. In *4 and *5, MB = 15 irrespective of MBE and MBS. *6 to *10 indicate addressable areas.
Description of the machine cycle column
S indicates the number of machine cycles required for skip operation by an instruction having skip function. The S value varies as follows: * When not skipped .............................................................................. S = 0 * When 1-byte or 2-byte instructions are skipped ............................ S = 1 * When 3-byte instructions are skipped ............................................. S = 2 Note GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle of CPU clock and five time periods are available according to PCC and SCC setting. (Refer to 4.2 (3) Processor clock control register (PCC).)
155
PD75237
Note
Mnemonic
Operands A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL
No. of Machine Bytes Cycle 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 1 1 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 3 3 3 An4 reg1n4 XAn8 HLn8 rp2n8 A(HL)
Operation
Addressing Area
Skip Condition Stack A
Stack A Stack B
*1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH
A(HL), then LL+1 A(HL), then LL-1 A(rpa1) XA(HL) (HL)A (HL)XA A(mem) XA(mem) (mem)A (mem)XA Areg XArp' reg1A rp'1XA A(HL) A(HL), then LL+1 A(HL), then LL-1 A(rpa1) XA(HL) A(mem) XA(mem) Areg1 XArp' XA(PC14-8+DE)ROM XA(PC14-8+XA)ROM XA(BCDE)ROM XA(BCXA)ROM
MOV @HL, A @HL, XA A, mem Transfer XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA A, @HL A, @HL+ A, @HL- A, @rpa1 XCH XA, @HL A, mem XA, mem A, reg1 XA, rp' XA, @PCDE Table reference MOVT XA, @PCXA XA, @BCDE XA, @BCXA
*1 *1 *1 *2 *1 *3 *3 L=0 L = FH
*11 *11
Note
Instruction Group
156
PD75237
Note 1
Mnemonic
Operand CY, fmem.bit
No. of Machine Bytes Cycle 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 1 2
Operation CY(fmem.bit) CY(pmem7-2+L3-2.bit(L1-0)) CY(H+mem3-0.bit) (fmem.bit)CY (pmem7-2+L3-2.bit(L1-0))CY (H+mem3-0.bit)CY AA+n4 XAXA+n8 AA+(HL) XAXA+rp' rp'1rp'1+XA A, CYA+(HL)+CY XA, CYXA+rp'+CY rp'1, CYrp'1+XA+CY AA-(HL) XAXA-rp' rp'1rp'1-XA A, CYA-(HL)-CY XA, CYXA-rp'-CY rp'1, CYrp'1-XA-CY AA n4 AA (HL) XAXA rp' rp'1rp'1 XA AA AA n4 (HL) rp' XA
Addressing Area *4 *5 *1 *4 *5 *1
Skip Condition
Bit transfer
CY, pmem.@L CY, @H+mem.bit MOV1 fmem.bit, CY pmem.@L, CY @H+mem.bit, CY A, #n4 XA, #n8 ADDS A, @HL XA, rp' rp'1, XA A, @HL ADDC XA, rp' rp'1, XA A, @HL SUBS XA, rp' rp'1, XA A, @HL SUBC XA, rp' rp'1, XA A, #n4 A, @HL AND XA, rp' rp'1, XA A, #n4 A, @HL OR XA, rp' rp'1, XA A, #n4 A, @HL XOR XA, rp' rp'1, XA
carry carry *1 carry carry carry *1
*1
borrow borrow borrow
Operation
*1
*1
*1
XAXA rp'1rp'1 AA AA n4
(HL) rp' XA
*1
XAXA rp'1rp'1
Note 2
RORC NOT
A A
CYA0, A3CY, An-1An AA
Note
1. Instruction Group 2. Accumulator manipulation
157
PD75237
Note
Mnemonic reg rp1 INCS
Operands
No. of Machine Bytes Cycle 1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1 1+S 1+S 2+S 2+S 1+S 2+S 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 regreg+1 rp1rp1+1
Operation
Addressing Area
Skip Condition reg = 0 rp1 = 00H
Increment/decrement
@HL mem reg DECS rp' reg, #n4 @HL, #n4
(HL)(HL)+1 (mem)(mem)+1 regreg-1 rp'rp'-1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY1 CY0 Skip if CY = 1 CYCY
*1 *3
(HL) = 0 (mem) = 0 reg = FH rp' = FFH reg = n4
*1 *1 *1
(HL) = n4 A = (HL) XA = (HL) A = reg XA = rp'
Compare
A, @HL SKE XA, @HL A, reg XA.rp'
Carry flag manipulation
SET1 CLR1 SKT NOT1
CY CY CY CY
CY = 1
Note
Instruction Group
158
PD75237
Note
Mnemonic
Operands mem.bit fmem.bit
No. of Machine Bytes Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2
Operation (mem.bit)1 (fmem.bit)1 (pmem7-2+L3-2.bit(L1-0))1 (H+mem3-0.bit)1 (mem.bit)0 (fmem.bit)0 (pmem7-2+L3-2.bit(L1-0))0 (H+mem3-0.bit)0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1 Skip if (pmem7-2+L3-2.bit(L1-0)) = 1 Skip if (H+mem3-0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7-2+L3-2.bit(L1-0)) = 0 Skip if (H+mem3-0.bit) = 0 Skip if (fmem.bit) = 1 and clear Skip if (pmem7-2+L3-2.bit(L1-0))=1 and clear Skip if (H+mem3-0.bit)=1 and clear CYCY (fmem.bit) CYCY (pmem7-2+L3-2.bit(L1-0)) CYCY (H+mem3-0.bit) CYCY (fmem.bit) CYCY (pmem7-2+L3-2.bit(L1-0)) CYCY (H+mem3-0.bit) CYCY CYCY CYCY (fmem.bit) (pmem7-2+L3-2.bit(L1-0)) (H+mem3-0.bit)
Addressing Area *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1
Skip Condition
SET1
pmem.@L @H + mem.bit mem.bit fmem.bit
CLR1
pmem.@L @H+mem.bit mem.bit fmem.bit
(mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0 (@H+mem.bit) = 0 (fmem.bit) = 1 (pmem.@L) = 1 (@H+mem.bit)=1
SKT Memory bit manipulation
pmem.@L @H+mem.bit mem.bit fmem.bit
SKF
pmem.@L @H+mem.bit fmem.bit
SKTCLR
pmem.@L @H+mem.bit CY, fmem.bit
AND1
CY, pmem.@L CY, @H+mem.bit CY, fmem.bit
OR1
CY, pmem.@L CY, @H+mem.bit CY, fmem.bit
XOR1
CY, pmem.@L CY, @H+mem.bit
PC14-0addr1 addr -- -- (Optimum instruction is selected from among BR !addr, BRA !addr1, BRCB !caddr and BR $addr1 by an assembler.) PC14-0addr1 PC140, PC13-0!addr PC14-0PC14-8+DE PC14-0PC14-8+XA PC14-0BCDE PC14-0BCXA PC14-0!addr1 PC14-0PC14, 13,12+caddr11-0 *11 *8 *11
5
Branch
$addr1 BR !addr PCDE PCXA BCDE BCXA BRA BRCB !addr1 !caddr
1 3 2 2 2 2 3 2
2 3 3 3 3 3 3 2
*7 *6
Note
Instruction Group 159
PD75237
Note
Mnemonic
Operands
No. of Machine Bytes Cycle
Operation (SP-5) (SP-6) (SP-3) (SP-4)PC14-0 (SP-2)x, x, MBE, RBE PC140, PC13-0addr, SPSP-6 (SP-5) (SP-6) (SP-3) (SP-4)PC14-0 (SP-2)x, x, MBE, RBE PC14-0addr1, SPSP-6 (SP-5) (SP-6) (SP-3) (SP-4)PC14-0 (SP-2)x, x, MBE, RBE PC14-00000, faddr, SPSP-6 x, x, MBE, RBE(SP+4) PC14-0(SP+1) (SP) (SP+3) (SP+2) SPSP+6 x, x, MBE, RBE(SP+4) PC14-0(SP+1) (SP) (SP+3) (SP+2) SPSP+6 then skip unconditionally x, PC14, 13, 12(SP+1) PC11-0(SP) (SP+3) (SP+2) PSW(SP+4) (SP+5), SPSP+6 (SP-1) (SP-2)rp, SPSP-2 (SP-1)MBS, (SP-2)RBS, SPSP-2 rp(SP+1) (SP), SPSP+2 MBS(SP+1), RBS(SP), SPSP+2 IME(IPS.3)1 IExxx1 IME(IPS.3)0 IExxx0 APORTn XAPORTn+1, PORTn PORTnA PORTn+1, PORTnXA Set HALT Mode (PCC.21) Set STOP Mode (PCC.31) No Operation
Addressing Area
Skip Condition
CALL
!addr
3
4
*6
CALLA
!addr1
3
3
*11
CALLF Subroutine stack control
!faddr
2
3
*9
RET
1
3
RETS
1
3+S
Unconditional
RETI
1
3
rp PUSH BS rp POP BS EI IExxx DI IExxx Input/output IN * A, PORTn XA, PORTn OUT * PORTn, A PORTn, XA CPU control HALT STOP NOP
1 2 1 2 2
1 2 1 2 2 2 2 2 2 2 2 2 2 2 1
Interrupt control
2 2 2 2 2 2 2 2 2 1
*
MBE = 0 or MBE = 1 and MBE = 15 must be set for execution of IN/OUT instruction Instruction Group
Note
160
PD75237
Note
Mnemonic
Operands RBn
No. of Machine Bytes Cycle 2 2 2 2 3 RBSn MBSn
Operation (n = 0 to 3) (n = 0, 1, 2, 3, 15)
Addressing Area
Skip Condition
SEL
MBn
* TBR instruction PC13-0(taddr)5-0+(taddr+1) ------------------------
GET1 *
taddr
1
PC140 -----------------------------------------------------------------* TCALL instruction (SP-5)(SP-6)(SP-3)(SP-4)PC14-0 4 (SP-2) x, x, MBE, RBE PC13-0(taddr)5-0+(taddr+1) SPSP-6, PC140 -----------------------------------------------------------------* (taddr) (taddr+1) instruction 3 executed in the case of instruction except TBR and TCALL instructions
5
Special
*10
-----------------------Depends on instructions referred to.
*
TBR and TCALL instructions are assembled pseudo-instructions to define the GETI instruction table. Instruction Group
Note
161
PD75237
8.3 (1)
OPERATION CODES Description of operation code symbols
R2 R1 R0 00 00 01 01 10 10 11 11 0 1 0 1 0 1 0 1
reg A X L H E D C B reg reg1
P2 P1 P0 00 00 01 01 10 10 11 11 0 1 0 1 0 1 0 1
reg-pair XA XA' HL HL' DE DE' BC BC' rp' rp'1
Q2 Q1 Q0 00 01 01 10 10 1 0 1 0 1
addressing @HL @HL+ @HL- @DE @DL @rpa1 @rpa
P2 P1 00 01 10 11
reg-pair XA HL DE BC rp1 rp2 rp
N5 N2 N1 N0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 1 0 1 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 0
IExxx IEBT IEW IETPG IET0 IECSI0 IE0 IE2 IE4 IEKS IE1
In : Immediate data for n4 and n8 Dn : Bn : Nn : Tn : Immediate Immediate Immediate Immediate data data data data for for for for mem bit n and IExxx taddr x 1/2
An : Immediate data for [Relative address distance from branch destination address (2 to 16)]-1 Sn : Immediate data for one's complement of [Relative address distance from branch destination address (15 to 1)]
162
PD75237
(2)
Operation codes of bit manipulation addressing *1 in the operand column indicates that the following three addressings are available. * fmem.bit * pmem.@L * @H+mem.bit The 2nd byte *2 of the operation code corresponding to the above addressing is shown below:
*1 fmem.bit
2nd Byte of Operation Code 1 1 0 1 1 0 B1 B0 F3 F2 F1 F0 B1 B0 F3 F2 F1 F0 0 0 G3 G2 G1 G0
Accessible Bits Manipulatable bits of FB0H to FBFH Manipulatable bits of FF0H to FFFH Manipulatable bits of FC0H to FFFH Manipulatable bits of accessible memory banks
pmem.@L @H+mem.bit
0 0
B1 B0 D3 D2 D1 D0
Bn : Immediate data for bit Fn : Immediate data for fmem (indicating the low-order 4-bits of address) Gn : Immediate data for pmem (indicating the bits 5 to 2 of address) Dn : Immediate data for mem (indicating the low-order 4 bits of address)
163
PD75237
Note 1
Operation Code Mnemonic Operands A, #n4 reg1, #n4 rp, #n8 A, @rpa XA, @HL @HL, A @HL, XA MOV A, mem XA, mem 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 1 0 0 1 0 0 1 1 1 1 1 1 0 0 0 1 0 1 1 1 1 1 0 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 1 1 1 1 1 B1 I3 1 1 I2 0 I1 1 I0 0 1 I3 I7 I2 I6 I1 I5 I0 I4 1 R2 R1 R0 I3 I2 I1 I0 B2 B3
P2 P1
0 Q2 Q1 Q0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0
1 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 0 1 0 1 0 0 0 0 0 1 1 1 1 1 0 1 0 1 1 1 1 1 R2 R1 R0 1 P2 P1 P0
Transfer
mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA A, @rpa XA, @HL A, mem XCH XA, mem A, reg1 XA, rp' XA, @PCDE
0 R2 R1 R0 0 P2 P1 P0
1 Q2 Q1 Q0 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 1
1 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 0
1 R2 R1 R0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 1 1 1 1 2 2 0 1 0 0 0 P2 P1 P0
Table reference
XA, @PCXA MOVT XA, @BCDE XA, @BCXA
Note 2
CY, 1 MOV1 1 , CY
Note
1. Instruction Group 2. Bit transfer
164
PD75237
Note 1
Operation Code Mnemonic Operands A, #n4 XA, #n8 ADDS A, @HL XA, rp' rp'1, XA A, @HL ADDC XA, rp' rp'1, XA A, @HL SUBS XA, rp' rp'1, XA A, @HL 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 1 1 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 1 1 0 0 1 1 B1 I3 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 I2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 I0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 P2 P1 P0 P2 P1 P0 1 1 0 0 0 1 1 1 0 0 0 1 1 0 I3 P2 P1 P0 P2 P1 P0 I2 I1 I0 1 1 0 0 0 1 0 0 0 1 1 0 1 0 I3 P2 P1 P0 P2 P1 P0 I2 I1 I0 1 1 0 1 1 0 1 1 1 1 1 1 1 0 I3 P2 P1 P0 P2 P1 P0 I2 I1 I0 1 1 1 1 1 1 0 0 1 0 P2 P1 P0 P2 P1 P0 1 1 1 1 0 0 1 1 1 0 P2 P1 P0 P2 P1 P0 1 1 1 1 0 0 0 0 1 0 P2 P1 P0 P2 P1 P0 I7 I6 I5 I4 I3 I2 I1 I0 B2 B3
Operate
SUBC
XA, rp' rp'1, XA A, #n4 A, @HL
AND XA, rp' rp'1, XA A, #n4 A, @HL OR XA, rp' rp'1, XA A, #n4 A, @HL XOR XA, rp' rp'1, XA Note 2 RORC NOT A A
Note
1. Instruction Group 2. Accumulator manipulation
165
PD75237
Note
Operation Code Mnemonic reg INCS rp1 @HL mem reg DECS rp' reg, #n4 @HL, #n4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 0 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 0 0 1 0 1 0 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 1 2 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 I3 0 1 I2 1 1 I1 1 0 I0 0 1 P2 P1 P0 0 R2 R1 R0 I3 I2 I1 I0 Operands 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 B1 0 R2 R1 R0 1 1 0 P2 P1 0 0 0 1 0 1 0 0 0 0 0 0 1 0 B2 B3
Increment/decrement
0 D7 D6 D5 D4 D3 D2 D1 D0
1 R2 R1 R0
Compare
A, @HL SKE XA, @HL A, reg XA, rp'
1 R2 R1 R0 1 P2 P1 P0
Carry flag manipulation
SET1 CLR1 SKT NOT1
CY CY CY CY mem.bit
B1 B0 0 0 1 1
SET1
1 mem.bit
B1 B0 0 0 1 1
0 D7 D6 D5 D4 D3 D2 D1 D0 0 2
Memory bit manipulation
CLR1
1 mem.bit
B1 B0 0 1 1 1
1 D7 D6 D5 D4 D3 D2 D1 D0 1 2
SKT
1 mem.bit
B1 B0 0 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1
0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 2 2 *2 *2 *2
SKF SKTCLR AND1 OR1 XOR1
1 1 CY, 1 CY, 1 CY, 1
Note
Instruction Group
166
PD75237
Note
Operation Code Mnemonic Operands !addr BR $addr1
(+16) to (+2) (-1) to (-15)
B1 1 0 1 1 0 1 1 1 1 1 1 0 1 1 1 0 0 1 0 1 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 0
B2 addr
B3
0 A3 A2 A1 A0 1 S3 S2 S1 S0 1 1 1 1 1 1 0 1 0 0 0 0 0 1 0 1 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 1 1 1 0 1 1 0 1 0 0 1 1 1 0 1 1 0 1 0 1 1 0 0 1 1 0 1 1 0 0 0 0 1 0 0 0 0 N1 N0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 faddr 1 0 1 0 0 caddr 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 1 addr addr1 addr1
5
Branch
BRA BRCB
!addr1 !caddr PCDE PCXA
BR BCDE BCXA CALL CALLA Subroutine stack control CALLF RET RETS RETI rp PUSH BS rp POP BS Input/output A, PORTn IN XA, PORTn PORTn, A OUT PORTn, XA EI IExxx 1 1 DI HALT STOP NOP RBn SEL MBn GETI taddr 1 0 0 0 1 N3 N2 N1 N0 T5 T4 T3 T2 T1 T0 IExxx 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 N5 1 1 1 1 N2 N1 N0 0 0 1 0 1 1 0 1 1 0 1 N3 N2 N1 N0 1 0 0 1 0 1 1 0 0 1 1 1 N3 N2 N1 N0 1 N3 N2 N1 N0 1 1 0 0 0 1 1 N3 N2 N1 N0 1 0 0 0 P2 P1 !addr !addr1 !faddr
0
P2 P1
CPU control Interrupt control
N5 1 1 1 0 1
1 N2 N1 N0 0 0 0 0 1 1 1 1
Note
Special
Instruction Group
167
PD75237
9. MASK OPTION SELECTION
The PD75237 has the following mask options enabling or disabling on-chip components.
Pin P40 to P43 Pull-up resistor incorporation enabled bit-wise P50 to P53 P70 to P73 S0/P120 to S3/P123 S4/P130 to S7/P133 S8/P140, S9/P141 S10/T15/P142, S11/T14/P143 S12/T13/P150/PH0 to S15/T10/P153/PH3 S16/P100 to S19/P103 Pull-down resistor incorporation to VLOAD or VSS bit-wise * S20/P110 to S23/P113 XT1, XT2 Deletion of sybsystem clock oscillator feedback resistor possible Pull-down resistor incorporation to VLOAD enabled bit-wise Pull-down resistor incorporation enabled bit-wise Mask Option
*
Select pull-down resistor incorporation to VLOAD or VSS in 8-bit units. In a system not using subsystem clocks, power consumption in the STOP mode can be decreased by removing the feedback resistor from the oscillator.
Note
168
PD75237
10. APPLICATION BLOCK DIAGRAM
Power Failure Detection
INT4 T0-T15
S0-S17
Electronic Tuner
LPF
PPO ANn
Fluorescent Display Panel (FIP) 18 Segments x 16 Digits
Hsync Pulse L Voice Lever R PORTn ANn
PD75237
Timer Tuner System Computer Remote Controlled Reception Hsync Detection PORT7 Key Matrix (18 x 4)
PC1490
INT0
LED
Remote Controlled Signal
OSD
SCK1 SO1
SCK0 SO0 PORTn BUZ X1 X2 XT1 XT2
Servo IC
Mechanism BZ Piozoelectric Buzzer 32.768 kHz
4.19/6.0 MHz
Remarks
LPF : Low Pass Filter OSD : On Screen Display Hsync : Horizontal Synchronous
169
PD75237
11.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 C)
PARAMETER Power supply voltage SYMBOL VDD VLOAD VI1 Input voltage VI2 VO VOD Except ports 4 and 5 Ports 4 and 5 Pull-up resistor TEST CONDITIONS RATING -0.3 to +7.0 VDD -40 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to +11 -0.3 to VDD +0.3 VDD -40 to VDD +0.3 -15 -15 -30 -30 -120 30 15 100 60 100 60 700 510 -40 to +85 -65 to +150
UNIT V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mW mW C C
Output voltage
Open-drain Pins except display output pins Display output pins 1 pins except display output pins S0 to S9, S16 to S23 1 pin
Output current high
IOH
T0 to T15
1 pin
Total of pins except display output pins Total of display output pins 1 pin Output current low IOL Total of ports 0, 2, 3 and 4 Total of ports 5 to 8 Total loss Operating temperature Storage temperature PT Topt Tstg Plastic QFP Peak value Effective value Peak value Effective value Peak value Effective value ( Ta = -40 to +70 C ) ( Ta = -40 to +85 C )
POWER SUPPLY VOLTAGE RANGE (Ta = -40 to +85 C)
PARAMETER CPU *1 Display controller Time/pulse generator Other hardware *1
TEST CONDITIONS
MIN. *2 4.5 4.5 2.7
MAX. 6.0 6.0 6.0 6.0
UNIT V V V V
* 1. 2.
Except the system clock osccillator, display controller and timer/pulse generator. The power supply voltage range varies, depending on the cycle time. Refer to the description of AC characteristics.
170
PD75237
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
RESONATOR RECOMMENDED CIRCUIT PARAMETER Oscillator frequency (fX) *1 TEST CONDITIONS VDD = Oscillation voltage range After VDD reaches the minimum value in the oscillation voltage range 2.0 VDD = 4.5 to 6.0 V 4.19 MIN. 2.0 TYP. MAX. 6.2 UNIT MHz
X1
Ceramic resonator
X2 C2
C1
Oscillation stabilization time *2
4
ms
X1
Crystal resonator
X2 C2
Oscillator frequency (fX) *1
6.2 10 30
MHz ms ms
C1
Oscillation stabilization time *2
X1
External clock
X2
X1 input frequency (fX) *1
2.0
6.2
MHz
PD74HCU04
X1 high and low level widths (tXH, tXL)
81
250
ns
* 1.
Oscillator characteristics only. Refer to the description of AC characteristics for details of instruction execution time. 2. Time required for oscillation to become stabilized after VDD application or STOP mode release.
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
RESONATOR RECOMMENDED CIRCUIT PARAMETER Oscillator frequency (fXT) *1 VDD = 4.5 to 6.0 V Oscillation stabilization time *2 10 s TEST CONDITIONS MIN. 32 TYP. 32.768
MAX. 35
UNIT kHz
XT1
Crystal resonator
XT2 R
1.0
2
s
C3
C4
XT1
External clock
XT2
XT1 input frequency (fXT) *1
32
100
kHz
XT1 high and low level widths (tXTH, tXTL)
5
15
s
* 1. 2.
Oscillator characteristics only. Refer to the description of AC characteristics for instruction execution time. Time required for oscillation to become stabilized after VDD application or STOP mode release.
171
PD75237
CAPACITANCE (Ta = 25 C, VDD = 0 V)
PARAMETER Input capacitance Output capacitance (except display output) Input /output capacitance Output capacitance ( display output ) SYMBOL CI CO CIO CO TEST CONDITIONS MIN. TYP. MAX. 15 15 15 35 UNIT pF pF pF pF
f = 1 MHz Unmeasured pin returned to 0 V
172
PD75237
DC CHARACTERISTICS (Ta = -40 to 85 C, VDD = 2.7 to 6.0 V)
PARAMETER SYMBOL VIH1 VIH2 VIH3 Input voltage high VIH4 Port 7 Except below Ports 0, 1, RESET, P81, P83 X1, X2, XT1 VDD = 4.5 to 6.0 V TEST CONDITIONS MIN. 0.7 VDD 0.8 VDD VDD-0.4 0.65 VDD 0.7 VDD Pull-up resistor incorporated 0.7 VDD Ports 4, 5 Open-drain VIL1 Input Voltage low VIL2 VIL3 Output voltage high VOH Except below Ports 0, 1 RESET, P81, P83 X1, X2, XT1 0.7 VDD 0 0 0 10 0.3 VDD 0.2 VDD 0.4 V V V V V V 0.4 2.0 0.4 0.5 0.2 VDD 3 VIN = VDD ILIH2 ILIH3 Input leakage current low Output leakage current high Output leakage current low ILIL1 ILIL2 ILOH1 ILOH2 ILOL1 ILOL2 IOD T0 to T15 RP7 RL RV1 Built-in pull-up resistor RV2 Port 7 VIN = VDD Display output Ports 0, 1, 2, 3, and 6 (except P00) VIN = 0 V Ports 4 and 5 VOUT = VDD -2.0 V X1, X2, XT1 Ports 4, 5 Except below VIN = 0 V X1, X2, XT1 Except below Ports 4, 5 Except below Display output S0 to S9, S16 to S23 Display output current VOUT = VDD (Open-drain) VOUT = 10 V VOUT = 0 V VOUT = VLOAD = VDD -35 V VDD = 4.5 to 6.0 V VOD = VDD -2 V VDD = 4.5 to 6.0 V -3 -15 20 20 VDD -VLOAD = 35 V VDD = 5 V 10% VDD = 3 V 10% VDD = 5 V 10% VDD = 3 V 10% 25 15 30 15 10 40 50 40 -5.5 -22 80 200 1000 135 80 300 70 60 -20 3 20 -3 -10 Open-drain VIN = 10 V 20 20 -3 V V V V TYP. MAX. VDD VDD VDD VDD VDD VDD UNIT V V V V V V
VIH5
All output pins VDD = 4.5 to 6.0V IOH = -1 mA VDD-1.0 except ports 4, VDD = 2.7 to 6.0V IOH = -100 A VDD-0.5 5 and P03 Ports 3, 4, 5 All output pins VDD = 4.5 to 6.0V IOL = 15 mA VDD = 4.5 to 6.0V IOL = 1.6 mA VDD = 2.7 to 6.0V IOL = 400 A Open-drain pull-up resistance 1k
Output voltage low
VOL
SB0, SB1 ILIH1 Input leakage current high Except below
A A A A A A A A A
mA mA k k k k k k k
Built-in pull-down resistor (mask option)
173
PD75237
DC CHARACTERISTICS (Ta = -40 to 85 C, VDD = 2.7 to 6.0 V)
PARAMETER SYMBOL IDD1 TEST CONDITIONS VDD = 5 V 10% *2 Operating 6 MHz crystal mode VDD = 3 V 10% *3 oscillation C1 = C2 = 22 pF VDD = 5 V 10% *4 HALT mode VDD = 3 V 10% Operating VDD = 5 V 10% *2 4.19 MHz crystal mode oscillation VDD = 3 V 10% *3 C1 = C2 = 22 pF VDD = 5 V 10% *4 HALT mode VDD = 3 V 10% 32 kHz crystal oscillation *5 Operating mode VDD = 3 V 10% MIN. TYP. 4.5 0.6 600 200 3 0.5 600 200 40 5 0.5 0.3 Ta = 25 C MAX. 13.5 1.8 1800 600 9 1.5 1800 600 120 15 20 10 5 UNIT mA mA
IDD2
A A
mA mA
IDD1 Supply current *1 IDD2
A A A A A A A
IDD3 IDD4
HALT mode VDD = 3 V 10% VDD = 5 V 10%
IDD5
XT1 = 0 V STOP mode
VDD = 3 V 10%
* 1. 2. 3. 4. 5.
Current flowing to the built-in pull-down (pull-up) resistor excluded. When operated in the high speed mode with the processor clock control register (PCC) set to 0011. When operated in the low speed mode with PCC = 0000. Subsystem clock oscillation included. When operated with subsystem clock with system clock control register (SCC) set to 1001 and the main system clock stopped.
A/D CONVERTER CHARATERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V, AVDD = VDD)
PARAMETER Resolution SYMBOL TEST CONDITIONS MIN. 8 2.5 V AVREF AVDD tCONV tSAMP VIAN RAN IAREF *2 *3 AVSS 1000 1.0 2.0 -10 Ta +85 C -40 Ta < -10 C TYP. 8 MAX. 8 1.5 2.0 168/fx 44/fx AVREF UNIT bit LSB
5
Absolute accuracy *1 Conversion time Sampling time Analog input voltage Analog input impedance AVREF current
s s
V M mA
* 1. 2. 3.
Absolute accuracy with any quantization error (1/2 LSB) excluded. Time until EOC = 1 after execution of conversion start instruction (fX = 28.0 s at 6.0 MHz, fX = 40.1 s at 4.19 MHz). Time until the end of sampling after execution of conversion start instruction (fX = 7.33 s at 6.0 MHz, fX = 10.5 s at 4.19 MHz).
174
PD75237
AC CHARACTERISTICS (Ta = -40 to +85 C , VDD = 2.7 to 6.0 V) (1) Basic Operation
PARAMETER CPU clock cycle time (minimum instruction execution time = 1 machine cycle) *1 SYMBOL TEST CONDITIONS Operation with main system clock VDD = 4.5 to 6.0 V MIN. 0.67 2.6 114 0 0 TI0 input high and lowlevel widths Interrupt input high and low-level widths RESET low-level width tTIH, tTIL tINTH, tINTL tRSL INT0 INT1, 2, 4 VDD = 4.5 to 6.0 V 0.48 1.8 *2 10 10 122 TYP. MAX. 64 64 125 1 275 UNIT
s s s
MHZ kHz
tCY
Operation with subsystem clock VDD = 4.5 to 6.0 V fTI
TI0 input frequency
s s s s s
* 1.
CPU clock () cycle time is determined by the oscillator frequency of the connected resonator, the system clock control register (SCC) and the processor clock control register (PCC). The cycle time tCY characteristics for power supply voltage VDD when the main system clock is in operation is
tCY VS VDD (Main System Clock in Operation) 70 64 60 6 5 4 Cycle Time tCY [s] 3 Operation Guaranteed Range
shown below. 2. 2tCY or 128/fX is set by interrupt mode register (IM0) setting.
2
1
0.5 0 1 2 3 4 5 6
Power Supply Voltage VDD [V]
175
PD75237
(2)
Serial Transfer Operation (a) 2-wire and 3-wire serial I/O mode (SCK...Internal clock output)
SYMBOL TEST CONDITIONS fX = 6.0 MHz VDD = 4.5 to 6.0 V fX = 4.19 MHz 1600 2680 3800 (tKCY/2)-50 (tKCY/2)-150 150 400 RL = 1 k CL = 100 pF* VDD = 4.5 to 6.0 V 250 1000 ns ns ns ns ns ns ns ns ns MIN. 1340 TYP. MAX. UNIT ns
PARAMETER
SCK cycle time
tKCY1 fX = 6.0 MHz fX = 4.19 MHz
SCK high and low level widths SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK
tKL1 tKH1 tSIK1 tKSI1 tKSO1
VDD = 4.5 to 6.0 V
*
RL and CL are SO output line load resistance and load capacitance, respectively. (b) 2-wire and 3-wire serial I/O mode (SCK...External clock input)
SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY2 3200 SCK high and low level widths SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK tKL2 tKH2 tSIK2 tKSI2 tKSO2 RL = 1 k CL = 100 pF* VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V 400 1600 100 400 300 1000 ns ns ns ns ns ns ns MIN. 800 TYP. MAX. UNIT ns
PARAMETER
*
RL and CL are SO output line load resistance and load capacitance, respectively.
176
PD75237
(c)
SBI mode (SCK...Internal clock output (master))
SYMBOL TEST CONDITIONS fX = 6.0 MHz VDD = 4.5 to 6.0 V MIN. 1340 1600 2680 3800 tKCY/2-50 tKCY/2-150 150 tKCY/2 RL = 1 k CL = 100 pF* VDD = 4.5 to 6.0 V 0 0 tKCY tKCY tKCY tKCY 250 1000 TYP. MAX. UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns
PARAMETER
SCK cycle time
tKCY3
fX = 4.19 MHz fX = 6.0 MHz fX = 4.19 MHz
SCK high and low level widths
SB0 and SB1 setup time (to SCK)
tKL3 tKH3 tSIK3 tKSI3 tKSO3
VDD = 4.5 to 6.0 V
SB0 and SB1 hold time (from SCK) SB0 and SB1 output delay time from SCK SB0, SB1 from SCK SCK from SB0, SB1 SB0 and SB1 low-level widths SB0 and SB1 high-level widths
tKSB tSBK tSBL tSBH
*
RL and CL are SO output line load resistance and load capacitance, respectively.
(d)
SBI mode (SCK...External clock input (slave))
SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V MIN. 800 3200 TYP. MAX. UNIT ns ns ns ns ns ns 300 1000 ns ns ns ns ns ns
PARAMETER SCK cycle time
tKCY4 tKL4 tKH4 tSIK4 tKSI4 tKSO4 RL = 1 k CL = 100 pF* VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V 400 1600 100 tKCY/2 0 0 tKCY tKCY tKCY tKCY
SCK high and low level widths
SB0 and SB1 setup time (to SCK)
SB0 and SB1 hold time (from SCK) SB0 and SB1 output delay time from SCK SB0, SB1 from SCK SCK from SB0, SB1 SB0 and SB1 low-level widths SB0 and SB1 high-level widths
tKSB tSBK tSBL tSBH
*
RL and CL are SO output line load resistance and load capacitance, respectively.
177
PD75237
AC Timing Test Points (Except X1 and XT1 Inputs)
0.8 VDD 0.2 VDD
Test Points
0.8 VDD 0.2 VDD
Clock Timing
1/fX tXL tXH
X1 Input
V DD - 0.5 V 0.4 V
1/fXT tXTL tXTH
XT1 Input
VDD - 0.5 V 0.4 V
TI0 Timing
1/fTI tTIL tTIH
TI0
178
PD75237
Serial Transfer Timing 3-wire serial I/O mode:
tKCY1 tKL1 tKH1
SCK
tSIK1
tKSI1
SI
Input Data
tKSO1
SO
Output Data
2-wire serial I/O mode:
tKCY2 tKL2 SCK tSIK2 tKSO2 tKSI2 tKH2
SB0,1
179
PD75237
Serial Transfer Timing Bus release signal transfer:
tKCY3,4 tKL3,4 tKH3,4
SCK tKSB tSBL tSBH tSBK tSIK3,4 tKSI3,4
SB0,1 tKSO3,4
Command signal transfer:
tKCY3,4 tKL3,4 tKH3,4
SCK tKSB tSBK tSIK3,4
tKSI3,4
SB0,1 tKSO3,4
Interrupt Input Timing
tINTL tINTH
INT0,1,2,4
RESET Input Timing
tRSL
RESET
180
PD75237
DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA HOLD CHARACTERISTICS (Ta = -40 to +85 C)
PARAMETER Data hold power supply voltage Data hold power supply current *1 Release signal set time Oscillation stabilization wait time *2
SYMBOL VDDDR IDDDR tSREL VDDDR = 2.0 V
TEST CONDITIONS
MIN. 2.0
TYP.
MAX. 6.0
UNIT V
0.1 0
10
A s
Release by RESET tWAIT Release by interrupt request
2 /fX *3
17
ms ms
* 1. 2. 3.
Current to the on-chip pull-up (pull-down) resistor is not included. Oscillation stabilization wait time is time to stop CPU operation to prevent unstable operation upon oscillation start. According to the setting of the basic interval timer mode register (BTM) (see below).
Wait Time BTM3 BTM2 BTM1 BTM0 (Values at fX = 6.0 MHz in parentheses) -- -- -- -- 0 0 1 1 0 1 0 1 0 1 1 1 220/fX (approx. 175 ms) 217/fX (approx. 21.8 ms) 215/fX (approx. 5.46 ms) 213/fX (approx. 1.37 ms) (Values at fX = 4.19 MHz in parentheses) 220/fX (approx. 250 ms) 217/fX (approx. 31.3 ms) 215/fX (approx. 7.82 ms) 213/fX (approx. 1.95 ms)
Data Hold Timing (STOP Mode Release by RESET)
Internal Reset Operation HALT Mode Operating Mode
STOP Mode Data Hold Mode VDD VDDDR STOP Instruction Execution RESET tWAIT tSREL
181
PD75237
Data Hold Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode STOP Mode Data Hold Mode Operating Mode
VDD
VDDDR STOP Instruction Execution
tSREL
Standby Release Signal (Interrupt Request) tWAIT
182
PD75237
12. CHARACTERISTIC CURVES (REFERENCE VALUES)
IDD vs VDD (Main System Clock : 6.0 MHz)
(Ta=25C)
5
5000
PCC=0011 PCC=0010 PCC=0001 PCC=0000 Main System Clock HALT Mode + 32 kHz Oscillation
1000
500
Power Supply Current IDD (A)
100
Subsystem Clock Operating Mode
50 Main System Clock STOP Mode + 32 kHz Oscillation and Subsystem Clock HALT Mode
10 X1 X2 XT1 XT2 330k 22pF
Crystal Resonator Crystal Resonator 32.768kHz
6.0MHz
5 22pF 22pF 22pF
1 0 1 2 3 4 5 6 7
Power Voltage VDD (V)
183
PD75237
IDD vs VDD (Main System Clock : 4.19 MHz)
(Ta=25C)
5000 PCC=0011 PCC=0010 PCC=0001 PCC=0000 Main System Clock HALT Mode + 32 kHz Oscillation
1000
500
Power Supply Current IDD (A)
Subsystem Clock Operating Mode 100
50 Main System Clock STOP Mode + 32 kHz Oscillation and Subsystem Clock HALT Mode
10 X1 X2 XT1 XT2 330k 22pF
Crystal Resonator Crystal Resonator 32.768kHz
4.19MHz
5 30pF 30pF 22pF
1 0 1 2 3 4 5 6 7
Power Voltage VDD (V)
184
PD75237
13. PACKAGE INFORMATION
94 PIN PLASTIC QFP (
20)
A B
F2
71 72
48 47
detail of lead end
C D
S
94 1
24 23
F1
G1
G2 H I
M
J K
P
N
NOTE
L
ITEM MILLIMETERS A B C D F1 F2 G1 G2 H I J K L M N P Q R S 23.20.4 20.00.2 20.00.2 23.20.4 1.6 0.8 1.6 0.8 0.350.10 0.15 0.8 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.10 3.7 0.10.1 5 5 4.0 MAX. INCHES 0.913 +0.017 -0.016 +0.009 0.787 -0.008 0.787 +0.009 -0.008 0.913 +0.017 -0.016 0.063 0.031 0.063 0.031 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.146 0.0040.004 55 0.158 MAX. S94GJ-80-5BG-3
Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
M
Q
R
185
PD75237
5
14. RECOMMEDED SOLDERING CONDITIONS
The PD75237 should be soldered and mounted under the conditions recommended in the table below. For soldering methods and conditions other than those recommended below, contact our salesman. Table 14-1 List of Recommended Soldering Conditions
Product Name
Package
Recommended Condition Symbol WS60-107-1 IR30-107-1 VP15-107-1 Pin part heating
PD75237GJ-xxx-5BG
94-pin plastic QFP
Table 14-2 Soldering Conditions
Recommended Condition Symbol
Soldering Method
Soldering Conditions Solder bath temperature: 260 C or less Duration: 10 sec. max. Number of times: Once Time limit: 7 days* (thereafter 10 hours prebaking required at 125 C) Preheating temperature: 120 C max. (package surface temperature) Package peak temperature: 230 C Duration: 30 sec. max. (at 210 C or above) Number of times: Once Time limit: 7 days* (thereafter 10 hours prebaking required at 125 C) Package peak temperature: 215 C Duration: 40 sec. max. (at 200 C or above) Number of times: Once Time limit: 7 days* (thereafter 10 hours prebaking required at 125 C) Pin part temperature: 300 C or less Duration: 3 sec. max. (Per device side)
WS60-107-1
Wave Soldering
IR30-107-1
Infrared reflow
VP15-107-1
VPS
Pin part heating
Pin part heating
*
For the storage period after dry-pack decompression, storage conditions are max. 25C, 65% RH. Use of more than one soldering method should be avoided (except in the case of pin part heating). For details of recommended soldering conditions for the surface mounting type, refer to the document "Semiconductor Device Mount Technology" (IEI-1207).
Note
Remarks
186
PD75237
APPENDIX A.
LIST OF PD75238 SERIES PRODUCT FUNCTIONS
Product Name
Item ROM RAM
PD75217
24448 x 8 768 x 4 0.95 s/1.91 s/ 15.3 s (Operation at 4.19 MHz)
PD75236
16256 x 8
PD75237
24448 x 8
PD75238
PD75P238
32640 x 8 1024 x 4
Main system clock selected Instruction cycle Subsystem clock selected I/O line FIP dual-function pin included and FIP dedicated pin excluded A/D converter High-voltage output FIP controller/ driver No. of segments No. of digits Timer Serial interface Interrupt source Operating temperature range Operating voltage Total Input Input/output Ouptut
0.95 s/1.91 s/ 3.82 s/15.3 s (Operation at 4.19 MHz)
0.67 s/1.33 s/2.67 s/10.7 s (Operation at 6.0 MHz)
122 s (Operation at 32.768 kHz) 33 8 20: 8 for LED drive 5 None 26: 40 V max. 9 to 16 segments 64 16 24: 12 for LED drive 24 8: 8-bit resolution 34: 40 V max. 9 to 24 segments 9 to 16 digits 4 channels 1 channel 3-wire 10 -40 to +85 C 2.7 to 6.0 V 94-pin plastic QFP 94-pin ceramic LCC with window 5 channels 2 channels SBI/3-wire 3-wire 11 -40 to +70 C
5
Package
64-pin plastic shrink DIP 64-pin plastic QFP
94-pin plastic QFP
187
PD75237
5
APPENDIX B.
DEVELOPMENT TOOLS
The following development tools are available for the development of systems using the PD75237. Language Processor
Ordering Code (Product Name)
Host Machine RA75X relocatable assembler
OS MS-DOSTM Ver.3.10 to Ver.3.30C PC DOSTM (Ver.3.1)
Supply Medium 3.5-inch 2HD 5-inch 2HD 5-inch 2HC
S5A13RA75X S5A10RA75X S7B10RA75X
PC-9800 series
IBM PC series
PROM Write Tools
PROM programmer which can easily program representative 256K-bit to 1M-bit PROMs and single-chip microcomputers with on-chip PROM from the keyboard or by remote control by connecting a board provided and a separately sold socket board. PROM programmer adapter for PD75P238 used in connection with PG-1500. PG-1500 is connected to the host machine via serial and parallel interfaces to control the PG1500 on the host machine. Software Ordering Code (Product Name)
Hardware
PG-1500
PA-75P238GJ
Host Machine PG-1500 controller PC-9800 series
OS MS-DOS Ver.3.10 to Ver.3.30C PC DOS (Ver.3.1)
Supply Medium 3.5-inch 2HD 5-inch 2HD 5-inch 2HC
S5A13PG1500 S5A10PG1500 S7B10PG1500
IBM PC series
188
PD75237
Debugging Tools
The IE-75000-R is an in-circuit emulator corresponding to the 75X series. Use the IE-75000-R and emulation probe in combinations for the development of PD75237. Debugging can be carried out efficiently by connecting the IE-75000-R to the host machine and the PROM programmer. The IE-75000-R-EM is an emulation board for the IE-75000-R and IE-75001-R. It is incorporated in the IE-75000-R. Use the IE-75000-R-EM and IE-75000-R or IE-75001-R in combinations for the evaluation of PD75237. The IE-75001-R is an in-circuit emulator corresponding to the 75X series. Use the IE-75001-R and emulation board IE-75000-R-EM which is sold separately, and emulation probe in combinations for the development of PD75237. Debugging can be carried out efficiently by connecting the IE-75001-R to the host machine and the PROM programmer. Emulation probe for PD75237 (94-pin plastic QFP). Used in combination with the IE-75000-R or IE-75001-R. 94-pin conversion socket EV-9200G-94 is also provided to facilitate connection with the user system. Controls the IE-75000-R and IE-75001-R on the host machine with the IE-75000-R and IE75001-R, connected to the host machine via RS-232-C. Software Ordering Code (Product Name)
IE-75000-R *
IE-75000-R-EM Hardware
IE-75001-R
EP-75238GJ-R
IE-9200G-94
Host Machine IE control program PC-9800 series
OS MS-DOS Ver.3.10 to Ver.3.30C PC DOS (Ver.3.1)
Supply Medium 3.5-inch 2HD 5-inch 2HD 5-inch 2HC
S5A13IE75X S5A10IE75X S7B10IE75X
IBM PC series
*
Maintenance product
189
190 Development Tool Configuration
In-Circuit Emulator Centronics I/F RS-232-C IE-75000-R-EM IE Control Program Host Machine PC-9800 Series IBM PC Series Symbolic Debugging Possible IE-75000-R IE-75001-R *1 EP-75238GJ-R Emulation Probe *2 PG-1500 Controller On-Chip PROM Product PROM Programmer User System
PD75P238GJ/KF
PG-1500
+ Relocatable Assembler Programmer Adapter
PA-75P238GJ
* 1. 2.
The IE-75001-R does not incorporate the IE-75000R-EM (sold separately).
PD75237
EV-9200G-94
PD75237
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Special Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. : Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. FIP (R) is a trademark of NEC Corporation. MS-DOSTM is a trademark of MicroSoft Corporation. PC DOSTM is a trademark of IBM Corporation.
M4 92.6

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